Poki Chen

Digital-to-time converter (DTC) or digital delay/timing generator has been developed for quite many years and plays a crucial role in automatic test equipment (ATE) and built-in self-test (BIST) industries. This study proposes a compact multidimensional delay array DTC based on phase shift in a phase-locked loop (PLL) to further extend field-programmable gate array (FPGA) applications into the analog domain. All internal delay cells are precisely controlled by PLL from the beginning to make the output phases distributed within the reference clock period as uniformly as possible. For further resolution enhancement, a hybrid structure based on PLL and a multidimensional delay array is presented to ensure high enough accuracy and substantially reduce logic utilization through phase sorting and selection. For concept proving, the proposed four-channel DTC is implemented on an Altera Stratix IV FPGA board to achieve 20 internal control bits, 2-ps resolution with very low integral nonlinearity (INL) and differential nonlinearity (DNL) of −2.06 to 2.01 and −2.50 to 2.31 LSB, respectively. In addition, the circuit has been successfully implemented on a much cheaper Cyclone IV platform also for cost reduction to achieve the same resolution with the best fine stage INL and DNL of −3.81 to 3.56 and −3.93 to 4.41 LSB, respectively. The DTC performance has demonstrated improvements to that of prior arts by one order finer resolution and higher accuracy compared to non-Vernier prior works, while eliminating the serious dead time issues inherent in Vernier DTCs.

Miniaturized fluxgate sensors typically use a lower number of coil turns due to technological limitations. Therefore, higher excitation frequencies are required to reach sufficient sensitivity. When using common materials, such as Vitrovac 6025F, the minimal thickness of the core is limited to 25 $\mathrm{\mu }$m, which is the only commercially available thickness of the amorphous tape. The penetration depth of a 1 MHz signal is around 6 $\mathrm{\mu }$m, which is much less than the thickness of the core. This leads to problems with saturating the core. Reaching deep saturation of the core requires high excitation current, which leads to excessive power consumption. Noise and perming are also increasing at high frequencies. In this paper, we show that the performance of the sensor can be greatly improved when using a 10 $\mathrm{\mu }$m thick core. The effect of eddy currents in the core is examined using FEM simulations, as well as measurements on the actual microfluxgate sensor.

This article presents an ultrasmall area on-chip relaxation oscillator with low-temperature sensitivity. In this design, a virtual resistor mainly composed of a complementary to absolute temperature (CTAT) voltage reference circuit is implemented to replace the real resistor for efficient temperature compensation, which counterbalances the inherent proportional to absolute temperature (PTAT) property of the original relaxation circuit of the oscillator. The conventional capacitor is also replaced with a MOS capacitor to complete the ALL-MOS oscillator circuit with two prime advantages, one of which is larger capacitance to area density, and the other is better matching with critical MOSFETs. Implemented in a 0.18- $\mu$ m TSMC standard CMOS process, the proposed relaxation oscillator has achieved a temperature coefficient of 28.17 ppm/ $^{\circ}$ C over the temperature range from $-$ 25 $^{\circ}$ C to $+$ 125 $^{\circ}$ C at 11.39-MHz oscillation frequency. This circuit consumes 243.1 $\mu$ W under 1.3-V power supply. Along with the abovementioned excellent performance, the oscillator achieves an ultrasmall core chip area of 0.009 mm $^{2}$ , which is almost one order less than most of the prior arts’ in the same process.

A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be realized at the same time. The input signal is fed into tapped delay lines (TDL) with regularized and automated cell placements to generate a multitude of delayed signals with plenty of regularized phase shifts. Due to periodicity, those phase shifts will be equivalently wrapped within a reference clock period and then phase sorting, ROM-based selection are applied to construct a merged TDL with uniform phase division across the reference clock period. The FPGA TDC was implemented successfully on both Altera Stratix IV to achieve a resolution as fine as 1ps with a measurement range of 1s. The short-range integral non-linearity errors (INL) are measured as -1.470 – 1.676 LSB for Stratix IV to demonstrate its excellent linearity.

As the techniques of autonomous driving become increasingly valued and universal, real-time semantic segmentation has become very popular and challenging in the field of deep learning and computer vision in recent years. However, in order to apply the deep learning model to edge devices accompanying sensors on vehicles, we need to design a structure that has the best trade-off between accuracy and inference time. In previous works, several methods sacrificed accuracy to obtain a faster inference time, while others aimed to find the best accuracy under the condition of real time. Nevertheless, the accuracies of previous real-time semantic segmentation methods still have a large gap compared to general semantic segmentation methods. As a result, we propose a network architecture based on a dual encoder and a self-attention mechanism. Compared with preceding works, we achieved a 78.6% mIoU with a speed of 39.4 FPS with a 1024 × 2048 resolution on a Cityscapes test submission.

This study proposes a 368 x 184 optical underdisplay fingerprint sensor designed and prototyped using the 0.11-μm CIS technology. The prototype sensor includes a hybrid array of global and rolling shutter pixels and a shared pixel-level analog-to-digital converter (ADC) embedded in a 32-pixel subarray configuration. It features a fast response time and low power consumption. By directly coupling the ramp signal to a floating diffusion capacitor with shared pixels, the best compromise between full-well capacity (FWC) and conversion gain is achieved. Two sets of memory (184 x 92 bytes) are also embedded in the pixel array to save the costs of external memory. A dynamic range of 110 dB is achieved with eight-segment automatic exposure and a contrast enhancement scheme for black level correction. A pixel binning process is used to improve the sensor sensitivity. The measured FWC, sensitivity, and conversion gain are 95 ke-, 800 ke-/lux-s, and 340 μV/e-, respectively. The prototype fingerprint sensor consumes only 15 mW with a 3.3-V supply voltage. The sensor chip size is 9.74 mm x 4.6 mm, and the sensing area is 8 mm x 4 mm, which is 71.4% of the chip size. The resolutions of the sensor without and with the pixel binning process are 1154 and 572 dpi, respectively.

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction flows, each of which performs fixed operational functions to create a 256-bit long instruction format. However, one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of dedicated compilers. Developing an architecture-specific compiler is really challenging. An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format. This scheduler is used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture is organized into six main stages, namely, fetch, instruction scheduler, decode, execute, data memory, and writeback. The complete design is verified, synthesized, and implemented on a Xilinx Virtex-6 (xc6vlx240t-1-ff1156). Maximum synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per cycle value that outperforms that of existing open-source RISC-V cores.