Zhenghao Lu
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Zhenghao Lu has a total of 69 co-authors. Here are the top co-authors by number of shared publications:
- Xiao-Peng Yu
Zhejiang University, Hangzhou, China
12 shared publications - Kiat Seng Yeo
School of Microelectronics, Tianjin University, Tianjin, CHINA
4 shared publications - Siqi Wang
Institute of VLSI Design, Zhejiang University, Hangzhou, China
4 shared publications Xiaopeng Yu
College of Integrated Circuits Zhejiang University Zhejiang China
4 shared publications- Liying Cai
Institute of VLSI Design, Zhejiang University, Hangzhou, China
3 shared publications - Xiong Song
Institute of VLSI Design, Zhejiang University, Hangzhou, China
3 shared publications
Latest Publications
- 15 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Sensors Letters
- Vol. 10 (2) , 1-4
A Low-Power BJT-Based CMOS Temperature Sensor Using a Common-Mode Error Suppression Sampling Scheme From −50 °C to 150 °C
A CMOS temperature sensor targeting automotive and industrial applications is presented. The sensor integrates a BJT-based sensing frontend with a second-order $\Sigma \Delta$ ADC. To address the accumulation of common-mode error in the integrator under low supply voltages, which can lead to large input common-mode deviations that reduce the integrator amplifier gain and degrade the ADC SNR, a novel sampling scheme is proposed. By means of a carefully designed sampling sequence, the proposed scheme maintains the amplifier input common-mode voltage within a small and predictable range, thereby stabilizing the amplifier gain and preventing SNR degradation. In addition, the sampling scheme reduces the number of ADC input branches, which effectively minimizes leakage current. To further enhance the measurement accuracy, a finite BJT current-gain compensation resistor and a bitstream-controlled dynamic element matching (BSC-DEM) technique are employed in the sensing frontend. Fabricated in a 180 nm CMOS process, the prototype achieves an inaccuracy of $\pm$1.0 °C (3$\sigma$) from −50 °C to 150 °C. The sensor consumes 6.3 μA from a 1.8 V supply at room temperature, achieves a resolution of 0.018 °C, and occupies an active area of 0.1 mm$^{2}$.
- 15 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Sensors Letters
- Vol. 10 (2) , 1-4
A Low-Power BJT-Based CMOS Temperature Sensor Using a Common-Mode Error Suppression Sampling Scheme From −50 °C to 150 °C
A CMOS temperature sensor targeting automotive and industrial applications is presented. The sensor integrates a BJT-based sensing frontend with a second-order $\Sigma \Delta$ ADC. To address the accumulation of common-mode error in the integrator under low supply voltages, which can lead to large input common-mode deviations that reduce the integrator amplifier gain and degrade the ADC SNR, a novel sampling scheme is proposed. By means of a carefully designed sampling sequence, the proposed scheme maintains the amplifier input common-mode voltage within a small and predictable range, thereby stabilizing the amplifier gain and preventing SNR degradation. In addition, the sampling scheme reduces the number of ADC input branches, which effectively minimizes leakage current. To further enhance the measurement accuracy, a finite BJT current-gain compensation resistor and a bitstream-controlled dynamic element matching (BSC-DEM) technique are employed in the sensing frontend. Fabricated in a 180 nm CMOS process, the prototype achieves an inaccuracy of $\pm$1.0 °C (3$\sigma$) from −50 °C to 150 °C. The sensor consumes 6.3 μA from a 1.8 V supply at room temperature, achieves a resolution of 0.018 °C, and occupies an active area of 0.1 mm$^{2}$.
- 10 January 2026
- Published by Wiley in Computer Applications in Engineering Education
- Vol. 34 (1)
A Project‐Based Learning Approach: Designing MATLAB‐Aligned Mixed‐Signal Circuit Components With Open Source Tools
This paper presents a project‐based learning approach to improve students' ability to apply systematic design methodologies during their transition from general Electrical Engineering (EE) courses to Integrated Circuit (IC) design programs. With the advent of Electronic Design Automation (EDA) tools and Artificial Intelligence (AI) techniques, there is a growing need for students to develop a more systematic understanding of circuit design. A structured training program is designed to enhance the ability of mixed IC design of fourth‐year students, who are expected to use open source tools to design key circuit components which are aligned with MATLAB. With these components, the mixed signal system can be built and optimized top‐down, allowing significantly accelerated development and deeper knowledge learning. A team of students is required to design MATLAB‐aligned circuit components and a benchmark testing framework is developed to ensure the alignment of functionality between the proposed work and MATLAB Simulink. The results indicate that the proposed project‐based learning approach effectively supports fourth‐year students in transitioning to IC design, with strong recommendations for its continued implementation in future academic years. The project establishes a comprehensive and free EDA framework for teaching mixed signal IC design, offering significant advantages over traditional commercial tools. Moreover, the use of hardware‐defined code provides greater flexibility in the design environment, allowing students to utilize the EDA framework across multiple platforms without the need for expensive commercial licenses.
- 10 January 2026
- Published by Wiley in Computer Applications in Engineering Education
- Vol. 34 (1)
A Project‐Based Learning Approach: Designing MATLAB‐Aligned Mixed‐Signal Circuit Components With Open Source Tools
This paper presents a project‐based learning approach to improve students' ability to apply systematic design methodologies during their transition from general Electrical Engineering (EE) courses to Integrated Circuit (IC) design programs. With the advent of Electronic Design Automation (EDA) tools and Artificial Intelligence (AI) techniques, there is a growing need for students to develop a more systematic understanding of circuit design. A structured training program is designed to enhance the ability of mixed IC design of fourth‐year students, who are expected to use open source tools to design key circuit components which are aligned with MATLAB. With these components, the mixed signal system can be built and optimized top‐down, allowing significantly accelerated development and deeper knowledge learning. A team of students is required to design MATLAB‐aligned circuit components and a benchmark testing framework is developed to ensure the alignment of functionality between the proposed work and MATLAB Simulink. The results indicate that the proposed project‐based learning approach effectively supports fourth‐year students in transitioning to IC design, with strong recommendations for its continued implementation in future academic years. The project establishes a comprehensive and free EDA framework for teaching mixed signal IC design, offering significant advantages over traditional commercial tools. Moreover, the use of hardware‐defined code provides greater flexibility in the design environment, allowing students to utilize the EDA framework across multiple platforms without the need for expensive commercial licenses.
- Open Access
A Low-Noise, Low-Power, and Wide-Bandwidth Regulated Cascode Transimpedance Amplifier with Cascode-Feedback in 40 nm CMOS
The dramatic growth in the emerging optical applications, including Lidar, short-range optical communication, and optical integrated sensing and communication (ISAC) calls for high-bandwidth transimpedance amplifiers (TIA) with low noise and low power in advanced CMOS technology nodes. To address the issues of existing TIA design, including the conventional RGC structure and the dual-feedback regulated cascode (RGC) TIA, design with complex feedback paths, i.e., limited bandwidth, extra noise, and high power consumption for enough bandwidth, this paper presents a novel TIA with the following key contributions. A novel RGC structure with cascode-feedback is proposed to increase feedback gain, thereby extending bandwidth and reducing noise. Design strategy of the proposed RGC TIA in a low-power advanced CMOS process is carried out to exploit weak inversion operation to achieve better power efficiency. Frequency response and noise analysis are also conducted to achieve target bandwidth and noise performance. The proposed TIA is designed and simulated in 40 nm CMOS with a target PD capacitance of 0.15 pF, achieving a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ. The average input-referred noise current spectral density is 18.3 pA/. Operating at 1.2 V, the core circuits consume only 6.6 mW, excluding the output buffer. Compared with prior RGC TIA designs, the proposed TIA achieves a 7.4×~243× enhancement in figure of merit.Open AccessA Low-Noise, Low-Power, and Wide-Bandwidth Regulated Cascode Transimpedance Amplifier with Cascode-Feedback in 40 nm CMOS
The dramatic growth in the emerging optical applications, including Lidar, short-range optical communication, and optical integrated sensing and communication (ISAC) calls for high-bandwidth transimpedance amplifiers (TIA) with low noise and low power in advanced CMOS technology nodes. To address the issues of existing TIA design, including the conventional RGC structure and the dual-feedback regulated cascode (RGC) TIA, design with complex feedback paths, i.e., limited bandwidth, extra noise, and high power consumption for enough bandwidth, this paper presents a novel TIA with the following key contributions. A novel RGC structure with cascode-feedback is proposed to increase feedback gain, thereby extending bandwidth and reducing noise. Design strategy of the proposed RGC TIA in a low-power advanced CMOS process is carried out to exploit weak inversion operation to achieve better power efficiency. Frequency response and noise analysis are also conducted to achieve target bandwidth and noise performance. The proposed TIA is designed and simulated in 40 nm CMOS with a target PD capacitance of 0.15 pF, achieving a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ. The average input-referred noise current spectral density is 18.3 pA/. Operating at 1.2 V, the core circuits consume only 6.6 mW, excluding the output buffer. Compared with prior RGC TIA designs, the proposed TIA achieves a 7.4×~243× enhancement in figure of merit. - 21 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Sensors Journal
- Vol. 25 (19) , 35687-35707
Triaxial MEMS Gyroscopes: A Review
As a fundamental component of inertial measurement, micro electromechanical systems (MEMS) gyroscopes are extensively utilized in industrial robotics, drones, and personal navigation systems. Triaxial MEMS gyroscopes, capable of simultaneously measuring angular rates along three axes and providing three-dimensional orientation, have garnered significant attention in recent years. This paper presents three contemporary integration methods for triaxial MEMS gyroscopes: 3D integration of three single-axis gyroscopes, the monolithic single-structure triaxial gyroscope, and the monolithic multi-structure gyroscope array. Furthermore, the methods are compared and analyzed, discussing their respective advantages and disadvantages, while the future applications and development trends of triaxial MEMS gyroscopes are explored.
- 21 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Sensors Journal
- Vol. 25 (19) , 35687-35707
Triaxial MEMS Gyroscopes: A Review
As a fundamental component of inertial measurement, micro electromechanical systems (MEMS) gyroscopes are extensively utilized in industrial robotics, drones, and personal navigation systems. Triaxial MEMS gyroscopes, capable of simultaneously measuring angular rates along three axes and providing three-dimensional orientation, have garnered significant attention in recent years. This paper presents three contemporary integration methods for triaxial MEMS gyroscopes: 3D integration of three single-axis gyroscopes, the monolithic single-structure triaxial gyroscope, and the monolithic multi-structure gyroscope array. Furthermore, the methods are compared and analyzed, discussing their respective advantages and disadvantages, while the future applications and development trends of triaxial MEMS gyroscopes are explored.
- 10 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 72 (11) , 6399-6410
An Ultrasound Transducer Analog Front-End With dB-Linear Time-Gain Compensation Using Translinear Loop Principle
This article presents an ultrasound analog front-end (AFE) circuit featuring continuous time-gain compensation (TGC) based on a variable-gain current amplifier (VGCA). The AFE comprises a class-AB input current buffer and a current gain stage realized by the translinear (TL) loop principle. The gain of the gain stage is precisely controlled by a novel exponential current generator to achieve the dB-linear gain characteristic. The proposed AFE is fabricated in a 0.13- $\mu $ m CMOS technology with a core area of 0.08 mm2. The measurement results show that the VGCA has a dB-linear gain range of 37.3 dB with a gain error of less than ±0.7 dB. Within the gain range, the VGCA consumes an average power of 0.65 mW from a 1.2V supply, with a minimum bandwidth of 1.61 MHz.
- 10 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 72 (11) , 6399-6410
An Ultrasound Transducer Analog Front-End With dB-Linear Time-Gain Compensation Using Translinear Loop Principle
This article presents an ultrasound analog front-end (AFE) circuit featuring continuous time-gain compensation (TGC) based on a variable-gain current amplifier (VGCA). The AFE comprises a class-AB input current buffer and a current gain stage realized by the translinear (TL) loop principle. The gain of the gain stage is precisely controlled by a novel exponential current generator to achieve the dB-linear gain characteristic. The proposed AFE is fabricated in a 0.13- $\mu $ m CMOS technology with a core area of 0.08 mm2. The measurement results show that the VGCA has a dB-linear gain range of 37.3 dB with a gain error of less than ±0.7 dB. Within the gain range, the VGCA consumes an average power of 0.65 mW from a 1.2V supply, with a minimum bandwidth of 1.61 MHz.
- Open Access
- 8 October 2024
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 14 (4) , 49
A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification
This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm2, and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234 W, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester.- 8 October 2024
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 14 (4) , 49
Open AccessA High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification
This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm2, and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234 W, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester. - Open Access
- 29 February 2024
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 14 (1) , 13
A Sub-1-V Nanopower MOS-Only Voltage Reference
A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40 C to 120 C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively.- 29 February 2024
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 14 (1) , 13
Open AccessA Sub-1-V Nanopower MOS-Only Voltage Reference
A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40 C to 120 C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively. - Open Access
- 30 December 2023
- Published by MDPI AG in Preprints.org
A Sub-1-V Nanopower MOS-Only Voltage Reference
A novel low-power MOS-only voltage reference is presented. The Enz-Krummenacher-Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the well-match between the current source stage and the output stage, the non-linear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed in 55 nm COMS technology. The operating temperature ranges from -40 ∘C to 120 ∘C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/∘C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and -89 dB respectively.
- 30 December 2023
- Published by MDPI AG in Preprints.org
Open AccessA Sub-1-V Nanopower MOS-Only Voltage Reference
A novel low-power MOS-only voltage reference is presented. The Enz-Krummenacher-Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the well-match between the current source stage and the output stage, the non-linear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed in 55 nm COMS technology. The operating temperature ranges from -40 ∘C to 120 ∘C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/∘C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and -89 dB respectively.
- Open Access
Design and Implementation of an Event-Driven Smart Sensor Node for Wireless Monitoring Systems
In this paper, an event-driven wireless sensor node is proposed and demonstrated. The primary design objective is to devise a wireless sensor node with miniaturization, integration, and high-accuracy recognition ability. The proposed wireless sensor node integrates two vibration-threshold-triggered energy harvesters that sense and power a threshold voltage control circuit for power management, a microcontroller unit (MCU) for system control, a one-dimensional convolutional neural network (1D-CNN) environment data analysis and vibration events distribution, and a radio frequency (RF) digital baseband transmitter with IEEE 802.15.4-/.6 protocols. The dimensions of the wireless sensor node are 4 × 2 × 1 cm3. Finally, the proposed wireless sensor node was fabricated and tested. The alarming time for detecting the vibration event is less than 6 s. The measured recognition accuracy of three events (knock, shake, and heat) is over 97.5%. The experimental results showed that the proposed integrated wireless sensor node is very suitable for wireless environmental monitoring systems.
Open AccessDesign and Implementation of an Event-Driven Smart Sensor Node for Wireless Monitoring Systems
In this paper, an event-driven wireless sensor node is proposed and demonstrated. The primary design objective is to devise a wireless sensor node with miniaturization, integration, and high-accuracy recognition ability. The proposed wireless sensor node integrates two vibration-threshold-triggered energy harvesters that sense and power a threshold voltage control circuit for power management, a microcontroller unit (MCU) for system control, a one-dimensional convolutional neural network (1D-CNN) environment data analysis and vibration events distribution, and a radio frequency (RF) digital baseband transmitter with IEEE 802.15.4-/.6 protocols. The dimensions of the wireless sensor node are 4 × 2 × 1 cm3. Finally, the proposed wireless sensor node was fabricated and tested. The alarming time for detecting the vibration event is less than 6 s. The measured recognition accuracy of three events (knock, shake, and heat) is over 97.5%. The experimental results showed that the proposed integrated wireless sensor node is very suitable for wireless environmental monitoring systems.
- Open Access
- 1 October 2023
- Published by Walter de Gruyter GmbH in Journal of Electrical Engineering
- Vol. 74 (5) , 413-421
Design of wide-band high-linearity transimpedance amplifier using standard CMOS technology
In this paper, the design methodology of a high-linearity wide-band transimpedance amplifier (TIA) for cable television (CATV) application is addressed. A simple four-stage topology is proposed to maintain a well-balanced linearity over a wide operating band. The regulated cascode (RGC) input stage is used to match an input impedance of 75 Ω, followed by a gain stage with enhanced bandwidth. The high-linearity output stage is able to drive the 75 Ω load directly with high output swing under a high supply voltage. The prototype is implemented with a standard 0.11μm CMOS process while occupying the silicon area of 0.034 mm 2 . The measurement results for the prototype show a peak gain of 76.6 dBΩ over a 3-dB bandwidth of 1.1 GHz with a considerably small gain ripple and an OIP 3 of 20.4 dBm. The whole test chip consumes 447 mW DC power and the measured average input-referred noise current spectral density is 7.9 pA Hz −1/2 up to 1 GHz.
- 1 October 2023
- Published by Walter de Gruyter GmbH in Journal of Electrical Engineering
- Vol. 74 (5) , 413-421
Open AccessDesign of wide-band high-linearity transimpedance amplifier using standard CMOS technology
In this paper, the design methodology of a high-linearity wide-band transimpedance amplifier (TIA) for cable television (CATV) application is addressed. A simple four-stage topology is proposed to maintain a well-balanced linearity over a wide operating band. The regulated cascode (RGC) input stage is used to match an input impedance of 75 Ω, followed by a gain stage with enhanced bandwidth. The high-linearity output stage is able to drive the 75 Ω load directly with high output swing under a high supply voltage. The prototype is implemented with a standard 0.11μm CMOS process while occupying the silicon area of 0.034 mm 2 . The measurement results for the prototype show a peak gain of 76.6 dBΩ over a 3-dB bandwidth of 1.1 GHz with a considerably small gain ripple and an OIP 3 of 20.4 dBm. The whole test chip consumes 447 mW DC power and the measured average input-referred noise current spectral density is 7.9 pA Hz −1/2 up to 1 GHz.