Yuan Gao

This article presents a software–hardware codesigned field-programmable gate array (FPGA)-based real-time electrocardiogram (ECG) classification system that combines methodological and practical innovations to achieve state-of-the-art performance with an ultracompact model. On the software side, we introduce a hardware-adaptive, configurable quantization-aware training (QAT) framework that enables layerwise precision assignment and flexible quantization, ensuring that the trained model is highly accurate and hardware-friendly even at ultralow bit widths. On the hardware side, we propose a resource-efficient FPGA accelerator featuring a streaming architecture and a cosine-approximated continuous wavelet transform (CWT) module, optimized for low-power and real-time inference. Implemented in an FPGA, we demonstrate that a six-layer Inception-ResNeXt (IRN) network can achieve 99.5% inference accuracy on the MIT-BIH ECG dataset with 200-mW dynamic power and 0.0767-mJ/inference energy efficiency.

This brief presents an edge-AIoT speech recognition system, which is based on a new spiking feature extraction (SFE) method and a PoolFormer (PF) neural network optimized for implementation on field-programmable gate array (FPGA) hardware. A Python-driven high-level synthesis (HLS) flow is adopted to accelerate software-to-hardware conversion for fast validation, demonstrating the potential of FPGA-based solutions in edge applications. This work provides a holistic end-to-end solution for ultralow-power speech recognition, leveraging HLS to bridge the gap between software and hardware development. Implemented in a Xilinx PYNQ-Z2 FPGA board, this optimized PF model achieved a speech recognition accuracy rate of 95.41% on the 35-class Google Commands dataset with a parameter count of 39k.

This paper presents a low-power, learnable digital audio feature extractor (AuFEx) for always-on keyword spotting (KWS) in edge devices. A noise-aware design flow is introduced to integrate the tuning of AuFEx parameters directly into the neural network classifier’s training process. This co-design approach enables the joint optimization of feature extractor and classifier within a unified framework. By incorporating noise during the training process, the system becomes more robust to variations in signal-to-noise ratio (SNR), maintaining high inference accuracy even with lightweight neural network classifiers. This design flow supports the design of both time-domain AuFEx (TD-AuFEx) and frequency-domain AuFEx (FD-AuFEx) for single-keyword wake-word detection (WWD) and 10-keyword KWS tasks, respectively. Implemented in a 40nm CMOS process, both TD-AuFEx and FD-AuFEx achieve over 2% accuracy improvement with the smallest size backend classifier. Specifically, the TD-AuFEx for WWD task achieves classifier size of 3.1k parameters with 494 nW power consumption and $375~\mu $ s latency. The accuracy is maintained between 96.2% – 97.9% for SNR in the range of 5 – 20 dB. The FD-AuFEx for 10-keyword KWS achieves classifier size of 6.39k parameters with $1.258~\mu $ W power consumption and 34.625 ms latency. The accuracy is maintained between 87.5% – 92.2% for SNR in the range of 5 dB - 20 dB, which is one of the highest compared to the other state-of-the-art designs.

This paper presents a low-power data acquisition (DAQ) chip tailored for impulsive charge sensing, featuring a comparator-gated dynamic acquisition (CG-DAQ) architecture. A dynamic comparator triggers both the gain stage and a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) through a shared timing path, enabling event-driven amplification and digitization. Programmable conversion gain ranging from 5 to 40 mV/pC is achieved by switching the sampling capacitance. Fabricated in TSMC 65 nm CMOS, the chip detects input charges from 0.01 to 36 pC, supports a signal bandwidth of 10 kHz to 100 kHz, and enables sampling rates up to 1 MS/s. It achieves an input-referred noise of 5.5 fC_rms and a peak signal-to-noise ratio (SNR) of 67 dB, all within a 54 μW power envelope and a compact 0.03 mm² core area. The proposed architecture facilitates accurate and energy-efficient charge-domain sensing for capacitive and piezoelectric sensor applications.

This paper presents a circuit-algorithm co-design framework for learnable analog front-end (AFE) in audio signal classification. Designing AFE and backend classifiers separately is a common practice but non-ideal, as shown in this paper. Instead, this paper proposes a joint optimization of the backend classifier with the AFE’s transfer function to achieve system-level optimum. More specifically, the transfer function parameters of an analog bandpass filter (BPF) bank are tuned in a signal-to-noise ratio (SNR)-aware training loop for the classifier. Using a co-design loss function L_BPF, this work shows superior optimization of both the filter bank and the classifier. Implemented in open-source SKY130 130nm CMOS process, the optimized design achieved 90.5%–94.2% accuracy for 10-keyword classification task across a wide range of input signal SNR from 5 dB to 20 dB, with only 22k classifier parameters. Compared to conventional approach, the proposed audio AFE achieves 8.7% and 12.9% reduction in power and capacitor area respectively.

This paper presents a discontinuous conduction mode (DCM) hysteretic buck converter for battery-powered Internet of Things (IoT) sensors. To reduce the quiescent power consumption, a duty-cycled comparator with delay compensation feedback loop is used in the zero current detector (ZCD). This feedback loop generates a self-calibrated comparator input offset to compensate for the comparator propagation delay. Additionally, a dynamic biasing scheme is applied to the hysteretic comparator to enhance the conversion efficiency under light load. The proposed buck converter was implemented in a 55-nm CMOS BCDLite process with an active area of 0.76 mm $ \times 0.69$ mm. With 310 nA quiescent current, this buck converter supports load currents in the range of $1~{\mu }$ A - 300 mA with output voltage 0.8 V - 2.2 V. In particular, greater than 90% efficiency is maintained for load current from $10~{\mu }$ A to 100 mA with 95.8% peak efficiency.

This work presents a high-linearity 2× time-interleaved (TI) current-steering (CS) digital-to-analog converter (DAC) facilitated by an on-chip calibration approach. In order to accurately analyze the impact of interleaving errors on high-resolution TI-DAC, a comprehensive function of spurious-free dynamic range (SFDR) is derived from time-domain modeling. Based on theoretical analysis, a foreground two-step calibration scheme with low-complexity circuits is proposed to address the issue of SFDR degeneration caused by narrowband locking. The calibration of gain error mismatch (GEM) can be achieved by efficiently compensating for the current sources of each sub-DAC (sDAC) in the proposed GEM loop. The amplitude of the TI spurs induced by duty-cycle errors (DCEs) exhibits an unimodal linear characteristic. Based on this characteristic, a compact cyclic-quantization circuit (CQC) combined with a uniform grid search algorithm is proposed to realize a high-precision calibration for DCE. A 14-bit 4-GS/s TI-DAC with the foreground on-chip calibration is realized in 65-nm CMOS. Measurement results demonstrate that with one single-tone calibration, the SFDR can be improved up to around 25 dB, achieving an SFDR $\ge$ 61 dB across the entire first Nyquist zone.

The miniaturization and real time imaging capability have always been the desired properties of photoacoustic imaging (PAI) system, which unlocked vast potential for personalized healthcare and diagnostics. While the imaging quality and resolution in such systems are inferior due to physics and system volume constraints, which limited its wide deployment and application. This paper proposes a novel platform to enhance the imaging quality of handheld PAI system in real time, integrating MultiResU-Net imaging enhancement algorithm with Ferroelectric random-access memory (FeRAM) crossbar array. The FeRAM crossbar array enables in memory computing, which is highly suitable for accelerating deep neural network where extensive matrix multiplications are involved. The hardware implementation of the algorithm is optimized for low-power operation on edge devices, a specifically designed algorithmic strategy is further introduced to accurately simulate the impact of hardware variation on the computation in the array with time complexity of O(mn). The feasibility and effectiveness of this method are demonstrated through simulation data (synthesized through physical model) and in vivo data, the experimental results demonstrate more than 10 times of imaging resolution improvement. The execution of neural network inference has been significantly accelerated and can be completed within a few microseconds, fully covering the imaging speed in handheld PAI system and satisfying the real time imaging capability. The whole platform can be integrated into a compact size of 25×25×20 cm³, which is a portable system with real time and high resolution imaging capability.

PoolFormer is a subset of Transformer neural network with a key difference of replacing computationally demanding token mixer with pooling function. In this work, a memristor-based PoolFormer network modeling and training framework for edge-artificial intelligence (AI) applications is presented. The original PoolFormer structure is further optimized for hardware implementation on RRAM crossbar by replacing the normalization operation with scaling. In addition, the nonidealities of RRAM crossbar from device to array level as well as peripheral readout circuits are analyzed. By integrating these factors into one training framework, the overall neural network performance is evaluated holistically and the impact of nonidealities to the network performance can be effectively mitigated. Implemented in Python and PyTorch, a 16-block PoolFormer network is built with $64\times 64$ four-level RRAM crossbar array model extracted from measurement results. The total number of the proposed Edge PoolFormer network parameters is 0.246 M, which is at least one order smaller than the conventional CNN implementation. This network achieved inference accuracy of 88.07% for CIFAR-10 image classification tasks with accuracy degradation of 1.5% compared to the ideal software model with FP32 precision weights.