Miron Kłosowski

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.

This paper presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp, neighboring pixels can exchange status information. During the conversion, the direction and step size of the counter are set globally to realize the corresponding coefficient of a convolution kernel. This technique does not slow down the conversion when used for small kernels (3W3) and does not significantly increase sensor noise. Convolution windows of arbitrary size can be implemented. The concept was verified in an experimental 64W64 imaging array implemented in 180 nm CMOS technology.

Contribution: While research indicates usefulness of remote laboratories in teaching of digital hardware systems, their main application is to complement stationary classes. This work presents a low-cost, scalable architecture that supports rapid transformation of teaching to a model based solely on remote access mechanisms. Background: Adaptation of online laboratory solutions from the literature to en-masse teaching of digital circuits is time-consuming and expensive. Solutions that permit cheap and rapid conversion of courses to remote environments seem to be of high value, especially when social distancing renders direct teaching impossible. Intended Outcomes: Demonstration of a flexible and cheap architecture that permits rapid transformation of digital circuits laboratories to the remote environment. Validation of system's performance and usefulness on a large group of students. Application Design: Remote digital circuits laboratories from the literature are designed to complement stationary classes. For successful teaching during pandemic, a low-cost, flexible, and efficient solution to online laboratory based on commonly available technologies is required. Findings: The proposed remote laboratory architecture enables rapid conversion of on-site teaching to online model, while supporting in-situ upgrades and functionality enhancements. The presented solution proved to be a convenient substitute for conventional laboratories during pandemic.

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-V_pp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-V_pp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

The paper presents pixel receivers for massively parallel transmission of video signal between capacitive coupled integrated circuits (ICs). The receivers meet the key requirements for massively parallel transmission, namely low-power consumption below a single μW, small area of less than 205 μm ² , high sensitivity better than 160 mV, and good immunity to crosstalk. The receivers were implemented and measured in a 3-D IC (two face-to-face stacked chips fabricated in CMOS 180 nm process). The maximum throughput of 20 Mbps of single receiver has been achieved using a return-to-zero (RZ) code. The static and dynamic power consumption of the single receiver are below 0.2 μW and 0.3 μW/MHz, respectively. The design approach for cost-effective inter-chip massively parallel transmission of photosensor signals with pulse position modulation (PPM) has been also performed. With this approach and the developed receivers it is possible to transfer between chips 9-10 bit images at a speed of over 1k fps.

Summary: In the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion time and achieve the optimal linearity. Owing to this, the pixel using a photodiode working in the integration mode achieves a linear photoconversion characteristics (irradiance to digital number), and the conversion period, which is determined by the darkest parts of a scene, is reduced by an order of magnitude comparing with known ADC solutions. The proposed conversion technique has been validated with the ASIC prototype of a CMOS imager containing photosensors integrated with the ADCs. The ASIC was fabricated in standard 0.18 μm CMOS technology. A specialized measurement system has been used to optimize linearity in the hybrid‐mode conversion (integral nonlinearity below 2 LSB). The conversion period has been reduced 15 times compared with the standard technique. Measurements confirm functionality of the proposed approach, implemented within a small pixel area.

In the paper, a power-efficient digital technique for gain and offset correction in slope ADCs has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by a specially prepared clock-enable pulse sequence. The paper describes the properties of ADCs utilizing this clock stopping technique, including power dissipation, integral and differential nonlinearity. The experimental validation has been performed for the ASIC implementation of the 128-pixel imager containing photo-sensors integrated with analog-to-digital converters. Finally, a modification is proposed that increases the accuracy of the gain correction. Measurements confirm functionality of the proposed approach. Reduction of the PRNU (to 0.4 LSB) has been achieved as well.

In this paper, a gray-scale CMOS image sensor (CIS) characterization system with an optimization feature has been proposed. By using a very fast and precise control of light intensity, based on the pulsewidth-modulation method, it is avoided to measure the illuminance every time. These features accelerate the multicriteria CIS optimization requiring many thousands of measurements. The system throughput is 2.5 Gb/s, which allows for capturing images from large arrays of the size 3000 × 3000 pixels at the rate of 25 frames/s, or small arrays (128 × 128) at the rate of 15000 frames/s. The efficient transfer of measurement data to the external software allows immediate presentation of optimization results in 3-D plots. The system automatically measures nonuniformity, spatial noise, temporal noise, signal-to-noise ratio, dynamic range, nonlinearity and image lag. A flat diffuser has been proposed as a cheaper alternative to an integrating sphere. This optical front-end is particularly useful for testing prototype CISs and vision-chips implemented in standard CMOS technologies as lowor medium-dynamic-range imagers.