Xinchun Lin

Due to the fragile overcurrent capability, it is necessary to embed the current limitation into the control system of the grid-forming (GFM) converter. In such regard, the GFM converter undergoes the transient mode switching during low voltage ride-through (LVRT), which reshapes the power angle characteristics. Previous studies have proven that the introduction of current limitation poses challenges to transient synchronization stability. However, the impact of the unfavorable nonlinear damping, and the current limitation mode in which the current reference vector does not coincide with the coordinate axes are usually ignored. This paper reveals that two current limitation modes will appear during entering and exiting current saturation under severe grid faults, both for the d-axis priority and q-axis priority current limitation algorithm. And the modes of each fault stage during LVRT are clarified. Furthermore, the synchronization characteristics of the GFM converter under severe faults are investigated by power angle trajectories considering both current limitation and nonlinear damping. Based on intuitive physical images, a CCT calculation method is proposed to quantitatively analyze the influence of control parameters, namely active power reference and droop coefficient, on transient synchronization stability. To improve the resynchronization ability of the GFM converter after faults, an enhanced-LVRT scheme is proposed by applying the redesigned current limitation strategy. Thanks to the introduction of the power angle feedback into the current limitation, this scheme is adaptive to various large disturbance events. Finally, simulations and experiments are conducted to validate the theoretical analysis.

As the grid‐connected interface device of wind and photovoltaic power generation, the voltage source converter (VSC) must pass the low voltage ride‐through (LVRT) test. However, existing literature demonstrates that under weak grid conditions, there is a possibility of severe fluctuations in the terminal voltage of VSC during transiting from the pre‐sag normal operation mode to the LVRT mode. Unfortunately, it will make VSC frequently enter and exit LVRT mode. In order to address the tricky problem of transient instability of VSC riding‐through severe grid voltage sag under the weak grid, in this paper, the full‐order large‐signal model of VSC is established first. Then, based on the established model, the analysis indicates VSC will face the risk of losing stability under the weak grid during LVRT due to current transients. By studying the impacts of low short circuit ratio (SCR) on the basin of attraction of the post‐sag equilibrium point, the intrinsic mechanism of VSC losing stability under weak grid conditions is revealed. Moreover, considering that the transient stability is related to the current control, the stability‐enhanced LVRT control ensuring both small‐signal stability and transient stability of VSC during LVRT is proposed. Finally, the correctness of the above theoretical analysis is verified by real‐time simulation

The standalone solar‐storage AC supply system is an efficient form of utilizing renewable energy. The solar‐storage supply system normally includes two types of converters, grid‐forming (GFM) and grid‐following (GFL) converters. Nevertheless, the incompatibility of the dynamic performance between the GFM and GFL converters due to different control schemes may introduce the transient instability risk to the solar‐storage supply system. To address this issue, it is extremely necessary to perform transient stability analysis and stability‐enhanced control for such a system. In this paper, a sixth‐order model of the dc‐link timescale for the solar‐storage supply system is developed, whose accuracy and applicability are verified by comparing with the detailed electromagnetic model. Based on the derived model, the analysis demonstrates that the solar‐storage supply system faces the potential risk of transient instability under large disturbances of sudden load variation, due to the mismatch of the transient response speeds between virtual excitation control of the GFM converter and dc voltage control of the GFL converter. The transient stability boundary of the system is quantitatively investigated, by depicting the basin of attraction of the post‐disturbance equilibrium point. Furthermore, from the perspective of improving the coordination of the transient behaviours between the GFM converter and the GFL converter, the parameters related to virtual excitation control and dc voltage control are designed to enhance the transient stability of the system. Time‐domain simulations and real‐time simulations are conducted to validate the theoretical analysis. DC–AC power convertors, microgrids, power system control, power system transient stability, renewable energy power conversion

In the transient process of the grid-connected converter (GCC), the existing research mainly focuses on the impact of the control loops. Little attention is paid to the transient stability issues driven by the imbalance between the input power and output power of GCC. This paper shows that the transient stability issues will still exist even if ignoring the dynamics of phase-locked loop (PLL) and current loop. In this paper, the models of the AC grid and the GCC are built under the assumption that the dynamics of the PLL and current loop are ignored. Then, by analyzing the transient process of GCC under non-severe remote voltage sag, the effects of the imbalance power on the transient stability of GCC are discussed. Moreover, for the GCC to operate stably after the transient process, there should be a maximum input power limit (MIPL) for GCC, and the imbalance power equation is applied in this paper to determine the transient stability of GCC. Furthermore, the effects of the current limitation on the transient stability of the GCC are also discussed. Finally, the theoretical analysis has been verified by means of simulations.

When a three-phase stand-alone inverter feeds several loads simultaneously, to ensure the high reliability and continuity of power supply for the large load network, the inverter needs to operate continuously, even during faulty conditions. Moreover, the inverter should provide large enough current by switching from voltage control mode (VCM) to current control mode (CCM) to trigger the circuit breaker connecting the short-circuit fault branch to recover the power supply. Therefore, when a load short-circuit fault occurs, the inverter will switch from VCM to CCM. In CCM, the short-circuit currents can be controlled by the current limiting strategy. Once the fault is cleared, to quickly supply the remaining loads, the output voltages should be restored to the rated voltage as soon as possible. However, the fast recovery process from the load short-circuit fault may cause significant voltage overshoot and oscillation. The voltage overshoot may lead to load damage, and the voltage oscillation may extend fault recovery time. To effectively solve above problems, the voltage overshoot introduced by large fault current and post-fault load impedance after fault clearance is firstly analyzed in this paper, then the suppression strategy based on the parallel virtual impedance is proposed; Secondly, the voltage oscillation introduced by the initial phase difference between the voltage references and the output voltages when the inverter switches from CCM to VCM is analyzed, and then the effective suppression strategy which can achieve seamless mode switching after fault clearance is proposed. Experimental results have been carried to verify the effectiveness of the proposed strategies.

Voltage-controlled three-phase three-leg (TPTL) inverters are widely applied in various occasions. The inverters are generally switched to the current-controlled mode to limit the fault currents when short-circuit faults happen. Under symmetrical fault, the inverter can be controlled as a symmetrical, three phase current source. However, the voltage limiting could happen under asymmetrical fault. As a result, the fault phase currents will be distorted and cannot be completely controlled. The switching devices could be damaged while the setting design and reliable action of the protection devices will be also greatly affected. Considering the voltage limiting is mainly caused by large load impedance of healthy phase under asymmetrical fault, the voltage limiting is avoided by reducing the load impedance by means of the virtual impedance in parallel with the output filter capacitor in this paper. As a result, the current limiting loop is not broken and the fault phase currents can be effectively controlled. In addition, the implementation of virtual impedance in control system and the influence of virtual impedance on the stability of system are also analyzed in detailed. The theoretical results are validated by experiments.

Three-phase three-leg inverter is one of the most popular topologies for inverters. When short-circuit fault occurs, the inverter is generally switched to the current-controlled mode from voltage-controlled mode to limit the fault currents. In this situation, the inverter becomes equivalent to a symmetric, three-phase, positive sequence current source. However, the voltage limiting may occur under asymmetrical fault. In this paper, a closed-loop model based on time-domain is originally developed as a means to investigate the fault current characteristics under asymmetrical fault. Based on the proposed model, a more intuitive insight into fault currents is presented as follows.1) The positive sequence fundamental component of three-phase currents can still track the symmetric current references. 2) The magnitude of fault phase currents (ignoring the harmonics) will vary between 1 and √3 times of magnitude of current limiting references. Based on the conclusion, although the magnitudes of fault phase currents can be reduced by adopting smaller current limiting references, the actual magnitudes of fault phase currents will still vary in a range depending on the load impendence of healthy phase. Therefore, the reliable action of the protection devices is greatly affected and the selective protection cannot be realized. Furthermore, in order to achieve completely controllable fault currents under asymmetrical fault, two alternative current limiting strategies are presented with reverse current limiting references, and with current limiting references based on the introduced phase angle regulation. The theoretical results are validated by simulations and experimental results.

In two parallel three-level T-type converters (3LT²Cs) with the sharing DC-bus and AC-bus directly, the neutral-point (NP) potential balancing and the zero-sequence circulating currents (ZSCCs) have to be considered to ensure normal operation of parallel system. In the conventional control scheme, the distribution factor of small vectors with SVPWM strategies (or the injected zero sequence voltage with SPWM strategies) has to carry out two tasks simultaneously: NP potential balancing and ZSCCs suppression. However, the common challenge is how to coordinately control ZSCCs and NP potential due to only one controllable degree of freedom for two different targets. In this paper, the conventional scheme is investigated comprehensively. Theoretical analysis shows that the control authority over ZSCCs and NP potential is limited. Furthermore, a coordinated control strategy is proposed as follows: the distribution factor of one converter is in charge of the common NP potential balancing with the auxiliary NP bus, while the distribution factor of the other converter is in charge of ZSCCs regardless of NP potential. Based on the previous strategy, the distribution factor of every individual converter only needs to control one target, achieving the independent control of NP potential and ZSCCs. In addition, the performance of the proposed strategy is also evaluated. Theoretical analysis shows that NP potential balancing and ZSCCs suppression can be achieved simultaneously in two parallel 3LT²Cs. Finally, the effectiveness of the proposed strategy is verified by experimental results.

The three-level neutral-point-clamped (NPC) inverter has attracted significant interest for high power/voltage applications, due to its significant advantages. A drawback of NPC inverter is that it is prone to voltage drifts and low-frequency voltage ripples of the neutral-point. In this paper, a novel control strategy of neutral-point balancing under SVPWM-based switching strategy is proposed which can be generally applied for all NPC inverters. Different from the previous control strategies, the proposed strategy utilizes a proportional resonant (PR) controller, which not only can eliminate voltage drifts, but also can minimize low-frequency voltage ripples at the same time. The effectiveness of the approach is documented by experiments obtained from a grid-tie three-phase NPC inverter.