Soonhoi Ha

In addition to the various requirements that a multi-robot framework should meet, swarm robotics applications also demand robustness, flexibility, and scalability. While several frameworks have been developed for multi-robot operation, they mostly fall short of adequately supporting some of these essential requirements. In this work, we introduce a novel multi-robot programming framework called HiSARM (High-level Specification, Automatic code generation, and Retargetable deployment for Multi-robot systems), designed to assist both mission planners and robot software developers. HiSARM employs a high-level language to enable mission planners to specify collaborative tasks among multiple robots intuitively. From these scripts written in a high-level language, executable robot code is automatically generated. Mission planners can easily customize the executable robot code according to their specific needs within HiSARM. Additionally, HiSARM provides multiple verification environments by introducing a formal intermediate representation and enabling retargetable deployment of the binary file across various domains, including simulation and real robots. For robot software developers, HiSARM eases the development process for robot software developers by categorizing software components and auto-generating swarm-related functions. We tested HiSARM with multiple scenarios in simulation and real robot environments, demonstrating that it effectively supports all the necessary features for multi-robot applications, including swarm operations.

The popularity of Linux in embedded systems has grown because of its reliability, flexibility, and performance. To ensure these systems meet specific real-time requirements, such as deadlines and throughput, Linux provides support for real-time schedulers and the PREEMPT_RT patch. However, while these tools prioritize high-priority tasks, they can inadvertently compromise the performance of other tasks. Completely Fair Scheduling (CFS) has served as the default scheduling policy in Linux until recently. The CFS is based on the principle that all runnable tasks should share the processor fairly, which helps balance task performance with overall system responsiveness. Despite its benefits, there has been no established method to assess whether real-time requirements are met under CFS. This paper introduces a novel analysis method to estimate the worst-case response time (WCRT) of tasks under CFS, providing a new solution for running real-time tasks in embedded Linux systems. Due to the dynamic nature of CFS, traditional WCRT analysis techniques are not applicable directly. Our technique analyzes how tasks sharing the same processor affect each other, focusing on their vruntime. By examining the bounds of vruntime variation and calculating the maximum interference from other tasks, we effectively estimate the WCRT. We also introduce algorithms that assign the nice values to tasks based on our proposed WCRT analysis technique, ensuring that the real-time requirements are met. We validate the proposed approach through comparative experiments using both a self-developed CFS simulator and an actual Linux system. Our simulator allows for rapid simulations and efficient exploration of various execution scenarios. Through extensive experiments, we empirically validate that our proposed analysis method is efficient with an acceptable level of overestimation. These make it a valuable tool for system verification and design optimization in Linux-based real-time systems.

The rapid advancement of Deep Learning (DL) models has led to a pressing need for efficient on-device DL solutions, particularly for edge devices with limited resources. Processing-In-Memory (PIM) technology 1 is considered a promising technology to address the worsening memory wall problem by integrating processing capabilities directly into memory modules. This paper evaluates the potential of Samsung PIM technology in enhancing the performance of on-device language inference. We assess the impact of PIM on the inference stage of three transformer models, Gemma 2, Qwen2 3, and TinyBERT 4 demonstrating an average 1.92× speed-up in endto-end latency compared to CPU by offloading all linear layers to PIM. Notably, Qwen2, which has characteristics favorable to PIM, achieves a 1.25× speed-up in end-to-end latency compared to GPU. Our findings emphasize the importance of understanding model characteristics for effective PIM deployment. The results demonstrate the PIM solution’s efficiency in enabling on-device language models and its edge deployment potential.

This tutorial article addresses a low power computer vision system as an example of a growing application domain of neural networks, exploring various technologies developed to enhance accuracy within the resource and performance constraints imposed by the hardware platform. Focused on a given hardware platform and network model, software optimization techniques, including pruning, quantization, low-rank approximation, and parallelization, aim to satisfy resource and performance constraints while minimizing accuracy loss. Due to the interdependence of model compression approaches, their systematic application is crucial, as evidenced by winning solutions in the Lower Power Image Recognition Challenge (LPIRC) of 2017 and 2018. Recognizing the typical heterogeneity of processing elements in contemporary hardware platforms, the effective utilization through parallelizing neural networks emerges as increasingly vital for performance enhancement. The article advocates for a more impactful strategy—designing a network architecture tailored to a specific hardware platform. For detailed information on each technique, the article provides corresponding references.