Hun-Seok Kim

This article presents MITTA, the first silicon-proven transformer accelerator optimized for multi-task inference across both natural language processing (NLP) and image processing domains. MITTA accelerates a task-sharing algorithm that minimizes sub-task computation by reusing both activations and weights from a shared base task, requiring only sparse delta computation for sub-tasks. To enhance efficiency, MITTA adopts block-wise structured sparsity (BSS) and INT8/INT4 mixed precision arithmetic, alongside a custom INT32 Softmax unit that avoids floating-point (FP) overhead while maintaining numerical accuracy and reducing power by 28%. To further optimize energy, MITTA implements a novel two-stage, task-adaptive dynamic voltage and frequency scaling (DVFS) scheme using a hierarchical power management architecture—combining off-chip DC–DC converters with on-chip power multiplexers (MUXes)—to dynamically select energy-optimal voltage–frequency operating points. Fabricated in 22-nm CMOS with a compact 5.8-mm² area, MITTA achieves 4.46TOPS/W (INT8) in its dense engine (DE) and up to 12.52TOPS/W (INT8) and 25.08TOPS/W (INT4) in its sparse engine (SE) at 0.55 V. Combined, task-sharing, DVFS, and INT4 arithmetic enable up to 77.8% energy savings and 90.1% latency reduction for sub-tasks such as human parsing (HP). Finally, quantitative results demonstrate that the proposed DVFS scheme significantly outperforms alternatives based on low-dropout regulators (LDOs), even when accounting for realistic DC–DC converter efficiency.

Rapidly evolving wireless channel conditions and communication standards demand adaptable forward error correction (FEC) decoders. Existing rigid architectures, designed for a single standard, exhibit limited adaptability in terms of throughput and/or coding gain, hindering the timely deployment of new applications. To overcome these limitations, we propose QFEC (quad-mode FEC decoder), a unified and highly configurable FEC decoder. QFEC enables a wide range of throughput vs. coding gain tradeoffs across QC-LDPC, Turbo, Polar, and Convolutional codes (CC) by providing full configurability for existing standards and proprietary systems. This ensures communication reliability under varying channel conditions and seamless support for both legacy and emerging communication protocols. Our hardware-unified approach leverages a shared memory and computation unit architecture that exploits the inherent commonalities in the iterative message-passing dataflow of all four code types. We attain outstanding flexibility at high data rates through an innovative combination of a fully customizable interconnect and a multi-mode computation datapath. The QFEC chip, fabricated in GF 12 nm FinFET technology, achieves 9.97 Gb/s throughput for the Optical Communication Terminal (OCT) standard and 6.52 Gb/s for 5G BG1, while consuming normalized energy efficiency (NEE) of 1.04 pJ/b and 1.53 pJ/b, respectively. This design can reach a maximum of 25.4 Gb/s using a proprietary QC-LDPC configuration. This design significantly surpasses existing solutions in flexibility by offering the broadest support for standards and parameters with a unified, efficient architecture. To the best of our knowledge, this is the first chip implementation of a fully flexible quad-mode FEC decoder for QC-LDPC, Polar, Turbo, CC codes.

This article presents a 256-point fast Fourier transform (FFT) processor based on an analog floating-point computation framework. A novel floating-point analog multiply-and-accumulate (FP-AMAC) unit encodes mantissas as pulse widths with a 4-bit digital exponent and operates through integrate, pulse, and reset stages with accuracy enhancements, including node pre-charge and comparator delay compensation. Implemented in 22-nm CMOS, the processor achieves 0.71–1.13 nJ/FFT at 1.53–1.94 GS/s, with a measured worst case output SNR of 31.37 dB, corresponding to a 12.3-bit fixed-point digital FFT. Post-silicon coarse-fine tuning and interpolation techniques ensure robust accuracy across process, voltage, and temperature (PVT) variations.

Deep learning-based joint source-channel coding (deep JSCC) has been demonstrated to be an effective approach for wireless image transmission. However, many current approaches utilize an autoencoder framework to optimize conventional metrics such as Mean Squared Error (MSE) and Structural Similarity Index (SSIM), which are inadequate for preserving the perceptual quality of reconstructed images. Such an issue is more prominent under stringent bandwidth constraints or low signal-to-noise ratio (SNR) conditions. To tackle this challenge, we propose DiffJSCC, a novel framework that leverages the prior knowledge of the pre-trained Stable Diffusion model to produce high-realism images via the conditional diffusion denoising process. First, our DiffJSCC employs an autoencoder structure similar to prior deep JSCC works to generate an initial image reconstruction from the noisy channel symbols. This preliminary reconstruction serves as an intermediate step where robust multimodal spatial and textual features are extracted. In the following diffusion step, DiffJSCC uses the derived multimodal features, together with channel state information such as the signal-to-noise ratio (SNR) and channel gain, to guide the diffusion denoising process through a novel control module. To maintain the balance between realism and fidelity, an optional intermediate guidance approach using the initial image reconstruction is implemented. Extensive experiments on diverse datasets reveal that our method significantly surpasses prior deep JSCC approaches on both perceptual metrics and downstream task performance, showcasing its ability to preserve the semantics of the original transmitted images. Notably, DiffJSCC can achieve highly realistic reconstructions for 768×512 pixel Kodak images with only 3072 symbols (<0.008 symbols per pixel) under 1dB SNR channels. The source code is available at https://github.com/mingyuyng/DiffJSCC.