Massoud Dousti

Purpose: This study proposes a fully differential, low-power, low-noise amplifier (LNA) with a 2nd-order Gm-C low-pass filter (LPF) for portable electroencephalogram (EEG) systems. The purpose of this study is to achieve an optimal noise-power tradeoff simultaneously minimizing input-referred noise (IRN) and power consumption. The study examines the impact of the proposed circuit design on the key parameters of EEG acquisition systems, particularly with regard to noise reduction and the overall system performance of an EEG system. Design/methodology/approach: The research methodology combines both theoretical analysis and postlayout simulations using 0.18-µm CMOS technology to design and evaluate the proposed LNA architecture. The LNA incorporates a fully differential chopper-stabilized recycling double-folded cascode (FDCRDFC) amplifier and a 2nd-order Gm-C LPF. Its performance is benchmarked against conventional fully differential folded cascode amplifiers to highlight gains in noise reduction and power consumption. Findings: The proposed LNA achieves a significantly reduced IRN of 0.62 µVrms over 0.1–100 Hz while consuming only 0.327 µW. The architecture has a mid-band gain of 64 dB and a bandwidth of 0.1–168 Hz, making it well-suited for portable EEG applications. The effective size of the proposed amplifier, including pads, is 560 × 560 µm2. Research limitations/implications: This study focuses on the amplifier’s design and its impact on noise reduction and power consumption. Further studies could explore the integration of multiple channels in high-density EEG arrays or active ripple suppression techniques using a chopper or tunable filtering for multimodal bio-signal acquisition. Practical implications: The significantly lower noise floor achieved by the proposed LNA enhances the signal quality in EEG acquisition systems, enabling more reliable real-time monitoring and improved accuracy in brain-health diagnostics. Originality/value: The principal originality of this study compared to traditional approaches, lies in the co-optimized integration of the three key techniques: a recycling double-folded cascode (RDFC) amplifier for enhanced gain-efficiency, an NMOS-based chopper modulator for 1/f noise cancelation and a weak-inversion Gm-C filter for ripple suppression. This synergistic approach achieves an exceptional noise-power tradeoff, which is the critical benchmark for next-generation portable EEG acquisition.

High data rate applications are becoming more popular every day. A small die area and low power consumption filters are essential for RF front‐end modules in order to achieve effective integration. This paper presents two small, on‐chip bandpass filters (BPFs) for 5G mm‐wave communication systems based on the second‐generation current‐controlled current conveyor (CCCII) using 32 nm carbon nanotube field‐effect transistors (CNTFET). The whale optimization algorithm is used for optimizing the current cut‐off frequency and port X parasitic resistance (R_X) of the designed CCCII. The first filter is designed for the 5G n258 band, with a center frequency of 24.25–27.5 GHz, and the second one is designed for the 5G n260 band, with a center frequency of 37–40 GHz. The novelty of these CNTFET‐based filters is that they are the first active filters, operating at the Ka‐band frequency with low power consumption and a tiny size.

This paper presents the design of an integrated wideband active coupler, using a universal structure designed for 45° and 180°, to realize arbitrary phase shifts below 90° and above 90°, respectively, by adjusting a pair of capacitors in the coupler. Furthermore, continuous phase shifts within the ranges of 180°–135° and 40°–90° are achieved. The variable capacitor in the passive network (PN) is implemented using variable capacitance, implemented by a transistor and by adjusting dimensions and gate‐source biasing. Each PN in the coupler is configured as a fifth‐order low‐pass filter, designed by transfer matrix analysis. A systematic design procedure based on this analysis is introduced, illustrating the combination of staggering technique, lumped‐element compensation, and multisection impedance transformation to provide low output phase error and improved directivity. Measurements conducted on fabricated chips in GaAs technology for the 180° (45°) coupler within the frequency range of 10–20 GHz reveal an output phase of 180° ± 1.5° (45° ± 1°), return loss better than 15 dB (15 dB), directivity greater than 30 dB (35 dB), and a coupling gain at the center frequency equal to 6 dB (5.2 dB). Continuously tunable output phase couplers for the phase ranges of 40°–90° and 180°–135° are achieved, based on the proposed universal structure, for each 2 GHz bandwidth in 12–14 GHz band. Within this frequency range, impedance matching around –10 dB and phase error of ± 1° are obtained. Comparable performance is observed in each 1 GHz sub‐band within the 14–20 GHz range. Additionally, simulation of the above couplers in 180 nm CMOS technology domonstrates similar performance.

In this research, we present a 16-bit multi-mode digital-to-analog converter (DAC) with a time-interleaved (TI) structure operating at a frequency of 4 GHz over a bandwidth (BW) of 20 MHz, which is in compliance with the fifth generation (5G) wireless communications. The proposed architecture uses only one clock frequency to generate radio frequency (RF) signals and includes a second-order (2nd-order) delta-sigma modulator (DSM) with a reconfigurable low-pass (LP) mode, band-pass (BP) mode at Fs/4, and high-pass (HP) mode for signal synthesis. To increase the sampling frequency (Fs) of the TI structure, four channels are proposed, each working at a frequency of Fs/4. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. This leads to design simplification, lower power consumption, smaller occupied area, and higher speed. A major challenge in designing this type of structure is the duty-cycle-error (DCE), especially in interleaved mode. In this research, we propose a new solution that solves DCE-related problems without adding digital circuits to the output of the DSM, by adjusting the analog filter circuit. Simulation results in MATLAB show that the value of signal-to-noise and distortion ratio (SNDR) in LP is equal to 106.14 dB, in BP is equal to 107.84 dB, and in HP is equal to 105.34 dB. Compensating for filters increases the spurious-free dynamic range (SFDR) to more than 118 dB.

A low-power and compact carbon nanotube field-effect transistor (CNTFET)-based [ ]-band electronically tunable band-pass filter (BPF) is presented. The filter is designed using second-generation multiple-output current-controlled current conveyor (MOCCCII). The presented active only current-mode BPF employs three MOCCCIIs and two CNTFETs as capacitors. This BPF can be tuned by varying the parasitic resistance of MOCCCIIs via the control current. The designed current-mode tunable BPF is simulated in an advanced design system (ADS) using the Stanford CNTFET model with the extension of noise and manufacturing process variation. The filter achieves a 21–23 GHz tuning frequency range, with a minimum noise figure of about 11.09 dB. The 1-dB compression point and input-referenced third-order intercept point are −19.28 and −8.4 dBm, respectively. This compact filter consumes only 145.7 [ ] W power at ± 0.5 V supply voltage at room temperature. The temperature analysis shows good thermal stability. The Monte Carlo analysis demonstrates the good process variation stability of the filter. The suggested BPF can be thought of as the first fully active BPF that is a candidate for [ ]-band communication applications with future advances in the fabrication process for CNTFET.