Meng-Hsueh Chiang

We investigate the fundamental electrical mechanisms driving non-ideal current behavior in NOR flash-based compute-in-memory (CIM) arrays. Measurements from an industrial 45 nm NOR flash process identify loading effects as the dominant degradation source. Unlike the conventional view that attributes loading primarily to bit-line voltage drop, we show it is more strongly governed by source-line voltage elevation from cumulative column current, leading to exponential drain current suppression consistent with subthreshold MOSFET theory. Experiments on a 64-cell test array confirm the model, revealing position-dependent current attenuation exceeding 40% under high-load conditions. These results directly link device-level physics to array-level performance limits, offering quantitative design guidelines for optimizing interconnect resistance, device parameters, and operating conditions in low-power CIM architectures for embedded artificial intelligence.

This study introduces a cross field-effect transistor (CrossFET) design, which features two orthogonally crossed transistors: an n-channel field-effect transistor (NFET) and a p-channel field-effect transistor (PFET). The CrossFET can function in three modes: pure NFET, pure PFET, and inverter, depending on the applied bias conditions. When operating purely as either an NFET or a PFET, the threshold voltage ( ${V} _{\text {t}}$ ) of the CrossFET can be precisely modulated by applying a specific voltage to the source and drain of the complementary transistor in the CrossFET. In the inverter mode, the NFET and PFET constitute an inverter. The simulation results indicate that the frequency of the CrossFET-based ring oscillator is 20% higher than that of the gate-all-around (GAA) FET-based counterpart for the same gate length because of the shared channel. The fabrication process of the CrossFET is compatible with that of GAA FETs. Both GAA FETs and CrossFETs can be implemented on the same wafer.

Thin-film transistors with ultrathin channels are fabricated and characterized at low temperatures down to 100 K in this study. Relying on a diffusive charge model, interfacial localized-state density and apparent carrier mobility are extracted from the measured data. The extraction is carried out by a numerical procedure based on particle swarm optimization (PSO). All the extracted parameters vary clearly with lowering temperatures ( $300\sim 100$ K), which are explained by phonon suppression, thermally-strained chemical bonds and carrier transport with effective mobility involving hopping mechanisms. This work demonstrates parameter extraction by PSO for the first time and highlights the challenges of non-crystalline transistors working at low temperatures.

A six-transistor (6T) static random access memory (SRAM) cell design comprising inserted-oxide fin field-effect transistors (iFinFETs) is compared against other 6T SRAM cell designs comprising either FinFETs, gate-all-around (GAA) nanowire field-effect transistors (NWFETs), or forksheet field-effect transistors (FSHFETs). The FSHFET and iFinFET SRAM exhibit better read stability, write ability, and lower minimum operating voltage ( ${V}_{\text {min}}{)}$ for the same cell size. To further reduce ${V}_{\text {min}}$ , we propose integrating high-current seven-nanowire iFinFETs with low-current three-nanowire NWFETs to achieve pull-up (PU):pass-gate (PG):pull-down (PD) ratio of 3:7:7. Due to a better PU ratio (0.41 versus 0.80), ${V}_{\text {min}}$ of 3:7:7 hybrid SRAM is reduced from 0.61 V of 7:7:7 iFinFET SRAM to 0.54 V without increasing the read or write access time. The static power consumption is reduced from 26 to 13 pW, and the dynamic power consumption is reduced from 117 to 101 nW due to lower gate capacitance and leakage current for the PU transistors.

A physical assessment of the lateral gate-all-around (GAA) nanosheet transistor (NSFET) at the G40M16 node (gate length = 12 nm projected for 2028) of the newly defined beyond-Moore International Roadmap for Devices and Systems [~5 nm node of the predecessor International Technology Roadmap for Semiconductors (ITRS)], supported by 3-D numerical device simulations and based on a proposed per-footprint scheme, is presented. The traditional evaluation scheme to gauge the performance of the transistor “per effective channel width” is shown to be improper due to pervasive bulk inversion. Bulk inversion, along the width of the nanosheet and at its ends, obfuscates the dependence of current on sheet/channel width and undermines the presumed added benefit of short-channel effect (SCE) control in the GAA device. The NSFET provides a flexible sheet width, as opposed to that of the FinFET with discrete fins, but the allowed range of sheet width is limited due to significant parasitic capacitance at a relatively narrow width and degraded SCE control and increased resistance for desired wide width. Furthermore, the nanosheet (NS) device density is undermined at a narrow width, especially for decreasing pitch. The FinFET is shown to be a favorable alternative to the NSFET even at the G40M16 node.

A high-permittivity (high- ${k}$ ) inserted-oxide FinFET (iFinFET) structure with low-permittivity inner spacers is proposed for CMOS transistor scaling to the 3-nm technology node and beyond. The process to fabricate an iFinFET is similar to the process to fabricate a nanosheet field-effect transistor (NSFET); no additional lithography masks are needed. Unlike the NSFET and the nanowire field-effect transistor (NWFET), which each require significant spacing between the nanosheets or nanowires (NWs) to accommodate metallic gate and dielectric insulator multilayer stacks, the iFinFET requires only a single ultrathin high- ${k}$ inserted-oxide (i-oxide) layer between the NWs, allowing more NWs to be vertically stacked within the constraint of a maximum total channel height. The i-oxide layers serve to allow fringing electric fields from the gate to penetrate into the NWs to achieve improved electrostatic integrity. Simulated performance characteristics of the proposed iFinFET structure are compared against those for the FinFET, NWFET, and NSFET. The iFinFET is projected to achieve the best electrical performance when the footprint (device layout width) is less than 80 nm.

In this work, an effective bilayer modulation is achieved for the multilayer hexagonal boron nitride (hBN) resistive random-access memory (RRAM) by an insertion of intentionally oxidized titanium oxide layer. The controllable multiple resistance states can be achieved by setting stop voltage of gradual RESET and compliance current during SET, which is beneficial for multilevel storage and neuromorphic application. The switching uniformity and the endurance of memory window are both improved by the effective bilayer modulation. Through experimental data and ab-initio calculation, both the switching and modulation mechanisms are clarified. The effective modulation can be attributed to the multiple thin conductive filaments with dual vacancies within the bilayer stacks of the multilayer hBN and titanium oxide. A significant formation energy difference between the two kinds of vacancy defects existing in bilayer stacks plays the key role for the filament formation through the fixed paths which benefits the switching uniformity. The findings gained from this work can help promote hBN in RRAM application.

Non-volatile resistive switching, also known as memristor¹ effect, where an electric field switches the resistance states of a two-terminal device, has emerged as an important concept in the development of high-density information storage, computing and reconfigurable systems^{2,3,4,5,6,7,8,9}. The past decade has witnessed substantial advances in non-volatile resistive switching materials such as metal oxides and solid electrolytes. It was long believed that leakage currents would prevent the observation of this phenomenon for nanometre-thin insulating layers. However, the recent discovery of non-volatile resistive switching in two-dimensional monolayers of transition metal dichalcogenide^10,11 and hexagonal boron nitride¹² sandwich structures (also known as atomristors) has refuted this belief and added a new materials dimension owing to the benefits of size scaling^10,13. Here we elucidate the origin of the switching mechanism in atomic sheets using monolayer MoS₂ as a model system. Atomistic imaging and spectroscopy reveal that metal substitution into a sulfur vacancy results in a non-volatile change in the resistance, which is corroborated by computational studies of defect structures and electronic states. These findings provide an atomistic understanding of non-volatile switching and open a new direction in precision defect engineering, down to a single defect, towards achieving the smallest memristor for applications in ultra-dense memory, neuromorphic computing and radio-frequency communication systems^2,3,11.

This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.