Guang-Li Luo

In this work, a plasma-free atomic layer deposition (ALD)-based H₂O post-treatment method is proposed to precisely modulate hydrogen-related (H-related) traps in indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) by the number of H₂O treatment cycles. Under the optimized condition, the scaled device with a channel length of 70 nm exhibits a near-ideal subthreshold swing of 62.9 mV/dec, a low threshold voltage (V_TH) of 0.18 V, an acceptable static leakage current, and a high drive current of 3.29 μA/μm at an overdrive voltage and drain voltage of 1 V. In addition, the treated device shows only a 13 mV of V_TH shift after 1000 s positive bias stress (PBS), corresponding to a 94% improvement compared with the pristine device. These improvements are attributed to the introduction of two different polarities of hydrogen-related traps after H₂O treatment. Furthermore, the influence of H-related traps on bias stability and the mechanisms responsible for V_TH shift are systematically clarified. These results establish that an optimized hydrogen incorporation window that maximizes the beneficial effects while balancing severe hydrogen-induced degradation caused by excessive hydrogen incorporation. Consequently, scaled IGZO TFTs with fast switching, low-power operation, high performance, and high reliability can be achieved, providing strong potential for back-end-of-line (BEOL)-compatible electronics and monolithic three-dimensional integrated applications.

The fabrication of heterogeneous p-SiGe/n-Si channel CFETs presents significant challenges. In a single fin structure, selectively etching the Si layer while preserving the SiGe layer for the p-FET and selectively etching the SiGe layer while preserving the Si layer for the n-FET requires two opposite etching steps. This process becomes particularly complex because of the additional local lithography required. In this study, CFETs with multiply stacked p-SiGe/n-Si nanosheet channels by using Ge interlayers as sacrificial layers are demonstrated based on the wafer-bonding process flow.

In this study, a high-κ HfO2/ZrO2 superlattice (SL-HZO) was utilized as the charge-trapping layer to develop a low-temperature polycrystalline silicon (LTPS)/SL-HZO GAAFET hybrid memory while removing the blocking oxide layer. The device was fabricated using green laser crystallization technology and low-temperature microwave annealing, ensuring compatibility with back-end-of-line processes. The LTPS/SL-HZO GAAFET operates at ±4 V/100 ns, achieving 106 cycles with minimal 12.5% memory window degradation and retention exceeding 10 years. Furthermore, the device demonstrates the potential for multi-bit storage and integrated logic operation capabilities. These features underscore its potential for in-memory computing and monolithic 3D integration applications.

This study presents a method for achieving stable morphotropic phase boundary characteristics in superlattice HfO2/ZrO2 (SL-HZO)-based metal-ferroelectric-metal (MFM) capacitors using low-temperature microwave annealing (MWA) technology. Compared to conventional rapid thermal annealing, MWA-treated SL-HZO-based MFM capacitors exhibit excellent dielectric properties (κ = 51) at reduced processing temperatures. These devices also demonstrate improved reliability, including lower leakage current, higher breakdown strength, and an operational lifetime exceeding 10 years at voltages up to 2.54 V. This approach mitigates thermal budget limitations in back-end-of-line processes while enhancing device performance, offering a promising solution for advanced integrated circuit applications.

This study investigated different layer thicknesses of HfO₂/ZrO₂ superlattice (SL HZO) as gate oxides. Metal-insulator-semiconductor (MIS) and metal-insulator-metal (MIM) capacitors were used to determine the optimal layer thickness of SL HZO for the further advancement of MOSFETs. The HfO₂/ZrO₂ layers are configured with thicknesses of 0.3 nm/0.3 nm, 0.5 nm/0.5 nm, and 1 nm/1 nm per layer. Compared to conventional solid-solution HZO thin films, SL HZO exhibits a higher dielectric constant, a lower interface trap density distribution, a smaller effective oxide thickness, and greater breakdown strength in the time-dependent dielectric breakdown test. In addition, the 0.3-nm SL HZO was used as the gate dielectric in Ge-stacked nanosheets gate-all-around field-effect transistors. The proposed device can achieve higher saturation current and improve the subthreshold swing than the device using HZO as the gate oxide..

This paper presents an advanced dielectric engineering approach utilizing a composition-dependent hafnium zirconium oxide (Hf_1-xZr_xO₂) superlattice (SL) structure for Si nanosheet gate-all-around field-effect transistors (Si NSGAAFETs). The dielectric (DE) properties of solid solution (SS) and SL Hf_1-xZr_xO₂ capacitors were systematically characterized through capacitance-voltage (C-V) and polarization-voltage (P-V) measurements under varying annealing conditions. A high dielectric constant (k-value) of 59 was achieved in SL-Hf_0.3Zr_0.7O₂, leading to a substantial reduction in equivalent oxide thickness (EOT). Furthermore, the SL-Hf_0.3Zr_0.7O₂ dielectric was integrated into Si NSGAAFETs, with the interfacial layer (IL) further optimized via NH₃ plasma treatment. The resulting devices exhibited superior electrical performance, including an enhanced ON-OFF current ratio (I_ON/I_OFF) reaching 10⁷, an increased drive current, and significantly reduced gate leakage. These results highlight the potential of SL-Hf_0.3Zr_0.7O₂ as a high-k dielectric solution for overcoming EOT scaling challenges in advanced CMOS technology and enabling further innovation in next-generation logic applications.

This article presents novel approach to achieving record low voltage, large memory window (MW), high speed, and endurance for high-density 1T nonvolatile memory (NVM) with N-type and P-type Fe-gate-all around field-effect transistors (GAAFETs) utilizing HfO₂/ZrO₂ superlattice (SL) dielectric and SiGe/Si SL channel for multibit memory. The proposed multibit Fe-GAAFETs exhibit a rapid switching speed of 100 ns and a substantial MW of approximately 2.5 V with an interfacial layer (IL) of SiO₂. Notably, P-type devices demonstrate write voltage at only 2 V, showcasing endurance exceeding 10⁷ cycles for each state, and a data retention time surpassing 10⁵ s, linearly extrapolated ten years without performance decrease and well-separated intermediate states. Additionally, the quantum well effect of the SiGe/Si SL channel is analyzed. These findings emphasize the feasibility of achieving low operating voltage for high-density 1T NVM applications.

This research investigates multibit ferroelectric FinFET (Fe-FinFET) utilizing SiGe/Si heterostructure superlattice (SL) channel. The SiGe/Si SL multibit Fe-FinFET exhibits a significant memory window (MW) of 1.53 V with SiO $_{\text{2}}$ for the interfacial layer (IL) and a rapid switching speed of 100 ns. A comparative analysis with the Si channel device was also conducted. Furthermore, the devices demonstrate the endurance of 10 $^{\text{4}}$ cycles, along with a retention duration surpassing 10 $^{\text{4}}$ s for each state, maintaining performance integrity over the equivalent of ten years of data retention at room temperature (RT) up to 85 $^{\circ}$ C. Additionally, basic physical analysis and simulations provide evidence that high mobility channels improve the MW and thermal stability. These results highlight the potential for low operating voltage in high-density 1T nonvolatile memory (NVM) applications.