Yi-Jan Emery Chen

This letter presents a 3.5-GHz fast-transient CMOS pulse modulator tailored for the application of wireless communication polar transmitters. The techniques of loop matching and shunt LC desensitization are used to effectuate the modulator’s wideband matching and absorptive characteristics. The measured insertion loss of the modulator is 2.2 dB, and the 3-dB bandwidth is 750 MHz, ranging from 3.03 to 3.78 GHz. The rise time and fall time of the modulated pulses are 0.9 and 0.62 ns, respectively. Tested with a 20-MHz 256-QAM 5G NR signal, the RF polar transmitter using the CMOS modulators can achieve the adjacent channel leakage ratio (ACLR) better than −35 dBc.

Conventional radio frequency (RF) transmitters frequently necessitate a pair of high-resolution, high-speed digital-to-analog converters (DACs) to ensure a specific level of linearity in wireless communication systems. Nevertheless, the high-resolution DACs escalate power consumption and area requirements and intensify the need for heat dissipation mechanisms. This paper presents a direct digital synthesis (DDS) transmitter using a pair of RF DACs with just 2 bits of resolution. The DDS transmitter, which uses a proposed digital pulse-width modulation signal with dithering, is resistant to power amplifier (PA) nonlinearity. Tested with 5G uplink signals and a pair of nonlinear PAs at 836.5 MHz, the transmitter could pass the stringent spectral requirements for 5G applications without using any digital predistortion or calibration techniques.

This letter presents the codesign of a 2.4-GHz CMOS rectifier and an antenna for efficiency enhancement at low input power. The RF differential-driven rectifier architecture is used to lower the driving voltage required to turn on the transistors. The high-resistance feedback path with an offset voltage is added to the rectifier circuit to reduce the reverse leakage current for efficiency enhancement. The rectifier is connected directly to the differential-feed antenna to eliminate the need and loss of a balun. The measured power conversion efficiency (PCE) of the rectifier achieves 63% at the input power of $-$ 8 dBm.

Antenna implementations at millimeter-wave (mmW) frequencies on printed circuit boards (PCBs) suffer a high dielectric loss due to long metal-feeding microstrips. Antenna-in-packages (AiPs) are practical solutions to shorten the lengths for power loss reduction. Also, 28 and 39GHz bands have been designated for the fifth generation (5G) of mobile communications. An active AiP covering these two bands is developed to provide dual-band and dual-polarization radiation based on the microstrip patch structure with parasitic elements to produce a second resonance. The large cross-polarization due to the mutual coupling between adjacent ports of dual-polarization is further suppressed by considering an image relation of elemental antennas’ orientations in the array composition. Numerical full-wave simulations and measurements over an antenna prototype are both shown to demonstrate the radiation where active transceiver modules were integrated. The examinations validate the feasibility of this AiP technique for 5G user equipment applications.

This article presents a dual-phase center-aligned 7-bit digital pulsewidth modulator for the envelope modulation of pulse-modulated polar transmitters (PMPTs). The digital pulsewidth modulator operates at a clock frequency and delivers the modulation frequency of 100 MHz. A delay-locked loop (DLL) consisting of 128 delay cells is used to generate the pulse edges for synthesis of center-aligned pulsewidth modulation (PWM) waveforms. The pulsewidth resolution is 78.1 ps. The measurement results show that the integral nonlinearity (INL) and differential nonlinearity (DNL) of the output pulses are within $\pm$ 0.4 and $\pm$ 0.3 LSB, respectively, in the duty cycle range of 2.12%–96.51%. Tested with a 20-MHz 256-quadrature-amplitude modulation (QAM) 5G new radio (NR) signal, the transmitter signal using the output of the modulator achieves the adjacent channel leakage ratio (ACLR) of $-$ 33.8 dBc.

This work presents a reconfigurable RF frequency synthesizer implemented with the field-programmable gate array (FPGA) and the digital-controlled oscillator (DCO) fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The frequency synthesizer uses a fractional frequency ratio calculator (FRC) to measure the DCO output frequency and realize frequency locking. Due to the FRC, the correlation of the DCO frequencies and its control codes can be characterized and stored in a lookup table (LUT) of the FPGA without the need of external measurement instruments. When requested to settle at a new frequency, the synthesizer looks for the DCO control code from the LUT and performs the frequency-locking routine. The synthesizer covers a wide frequency output range from 496 to 2470 MHz with the resolution of 195 kHz and achieves a settling time of 32.5–45 ns.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

An envelope tracking supply converter was presented for the RF power amplifiers of sub-6 GHz 5G NR mobile devices. The hybrid supply converter consisted of a linear, fast switching, and slow switching regulators connected in parallel. The two-phase hysteretic control was proposed for use in the fast switching regulator to track the fast-varying envelope of 40-MHz 5G NR signal. The 0.25-um CMOS supply converter achieved a maximum efficiency of 79.1%. The power-added efficiency improvement of the RF power amplifier with the proposed supply converter was 3.1% when tested with a 40-MHz 256-QAM 5G NR signal.