Niklas Rorsman

Understanding lateral heat transport in GaN high‐electron‐mobility transistors (HEMTs) is essential for the thermal management of high‐power and high‐frequency electronics. Here, lateral thermal transport in GaN HEMTs on 4H‐SiC is investigated using electrical thermometry. Nonlocal temperature transients are measured using a pulse I–V technique combined with on‐chip resistance thermometry, enabling high temporal and temperature resolution at lateral separations up to 424 from the heated channel. The employed technique resolves diffusion‐controlled transient lateral heat transport, enabled by Joule‐heating pulses that are approximately one order of magnitude shorter than the characteristic thermal diffusion time. Three‐dimensional (3D) finite‐element simulations are combined with the measurements to interpret the transient thermal response and identify the effective lateral thermal diffusion time of the device structure. The analysis further reveals strong lateral thermal coupling between the GaN epilayer and the 4H‐SiC substrate, demonstrating that substrate heat spreading dominates the transient thermal transport. These findings provide a quantitative framework for understanding heat propagation in GaN HEMTs and establish practical guidelines for the thermal design and optimization of next‐generation RF and power electronic technologies.

This work investigates gate-length (LG) scaling of AlGaN/GaN high electron mobility transistors (HEMTs) for cryogenic low-noise radio frequency (RF) operation at 4 K, targeting applications in radio astronomy receivers and quantum readout front ends. Devices with LG ranging from 1 down to 0.15 μm are characterized and analyzed using a delay-time framework to connect transport dynamics to RF and noise performance. The shortest gate tested device achieves a minimum noise temperature (Tmin) of 6 K at 5 GHz at 4 K, representing approximately an order of magnitude improvement compared to room temperature operation (300 K). The analysis indicates that enhanced effective electron velocity and reduced access resistances drive the observed improvements in RF and noise performance with both LG downscaling and cryogenic cooling while also revealing a growing influence of short-channel effects and parasitics at cryogenic temperatures. These results provide practical design guidelines for pushing GaN HEMTs toward lower noise through continued scaling and targeted optimization of access and contact resistances.

The high-voltage operation of GaN power high-electron mobility transistors (HEMTs) is primarily limited by electric field crowding near the gate field plates, which, over time, can degrade the dielectric properties of the passivation layer or gate insulators and compromise device reliability. Therefore, understanding the different breakdown mecha-nisms—X;their causes and locations—X;is essential for optimizing device design and improving off-state performance. Previous studies have primarily focused on device reliability in GaN HEMTs with doped buffer layers. By contrast, this study fo-cuses on the effects of prolonged off-state stress in Metal-Insu-lator-Semiconductor (MIS)-gated GaN HEMT with an Al-GaN/GaN/AlN heterostructure design without a buffer layer. The devices are investigated using electrical characteriza-tion, nanoscale structural/chemical analysis (SEM, TEM, EDS). Additionally, technology computer-aided design (TCAD) simulations are employed to describe the breakdown process by studying the electric field and charge distribution in the dielectrics. Based on the structural/chemical analysis, as well as the TCAD simulation results, it is suggested that the formation of a vertical percolation path in the SiNx passivation layer underneath the field plate edge initiates the destructive breakdown process.

This article investigates trapping mechanisms in AlGaN/GaN high electron mobility transistors (HEMTs) at cryogenic temperatures (CTs) down to 4.2 K, using pulsed I–V and drain current transient spectroscopy (DCTS) measurements. The results revealed an overall increase of trapping effects at CT. In particular, a substantial increase in current collapse at low temperatures was observed and predominately ascribed to deep acceptor states stemming from the iron (Fe)-doped GaN buffer. In contrast, devices with undoped buffer presented limited signs of trapping, which were only linked to surface and access regions. The aggravation at low temperatures of trapping effects was linked to a slower detrapping dynamic at low temperatures. Furthermore, the incorporation of gate field plates (FPs) led to a substantial attenuation of trapping and reduction of current collapse by a factor of 2.6 at CT in Fe-doped devices. These latter features were ascribed to the ability of the FP to decrease the electrical field along the device, highlighting the increased impact of FP at CTs. The results suggest that an undoped buffer with optimized gate FP could help to improve the reliability of GaN devices at low temperatures.

Assessing short channel effects (SCEs) is crucial in the high-frequency optimization of downscaled field-effect transistors (FETs) such as GaN high electron mobility transistors (HEMTs). Drain-induced barrier lowering (DIBL) is commonly used for quantifying the ability of the gate to modulate the drain–source current at high drain voltages. DIBL is traditionally extracted from the relative shift of the threshold voltage at different drain–source voltages. In this article, we propose a new method based on a drain current injection technique (DCIT) to assess DIBL. This method facilitates a direct measure of the threshold voltage over a wide range of drain–source voltages in a single measurement. The method is demonstrated and compared to the conventional method using AlGaN/GaN and InAlGaN HEMTs with a Fe-doped buffer and a $\textit{C}$ -doped AlGaN back-barrier, respectively. Furthermore, the impact of different gate lengths and GaN channel layer thicknesses is presented. The measurements are analyzed and discussed with supporting technology computer-aided design (TCAD) simulations. The proposed method facilitates a more general and detailed measurement of the DIBL for HEMTs.

Ultra-thin high-Al content barrier layers can enable improved gate control and high-frequency operation of AlGaN/GaN high electron mobility transistors (HEMTs) but the precise composition control is very challenging. In this work, we investigate the compositional profiles of AlxGa1−xN/GaN HEMT structures with targeted Al content in the barrier layer, x = 0.50, 0.70, and 1, and thickness in the sub-10 nm range in correlation with the two-dimensional electron gas (2DEG) properties. The HEMT structures are grown by metal-organic chemical vapor deposition on SiC. The maximum Al content in the barrier layer, experimentally determined by scanning transmission electron microscopy combined with energy-dispersive x-ray spectroscopy, is found to be lower than that intended and the deviations from the designed structures increase progressively with increasing x. Compositionally sharp interface between GaN and Al0.46Ga0.54N and box-like Al profile is achieved for intended x∼0.50 while pronounced Al grading is found in the samples with intended x of 0.70 and 1, with a maximum Al content of 0.78 reached for the HEMT structure with intended AlN barrier layer. The impact of the experimentally determined Al profiles on the 2DEG properties, obtained by contactless and electrical Hall effect measurements and coupled with self-consistent solution of the Poisson–Schrödinger equation, is evaluated and discussed. It is shown that the observed deviations from the intended Al profiles have a negative effect on the 2DEG confinement and result in reduced mobility parameters, which have significant implications for the implementation of high-Al content AlGaN/GaN structures in high-frequency devices.

The impact of different carbon concentrations in the Al0.06Ga0.94N graded back-barrier and GaN buffer of high electron mobility transistors (HEMTs) is investigated. Four epi-wafers with different carbon concentrations, ranging from $1\times 10^{{17}}$ to $5\times 10^{{17}}$ cm $^{-{3}}$ , were grown by metal organic chemical vapor deposition (MOCVD). HEMTs with 100 and 200 nm gate lengths were fabricated and characterized with dc, Pulsed-IV, drain current transient spectroscopy (DCTS), and large-signal measurements at 30 GHz. It is shown that the back-barrier effectively prevents buffer-related electron trapping. The highest C-doping provides the best 2DEG confinement, while lower carbon doping levels are beneficial for a high output power and efficiency. A C-doping of $1\times 10^{{17}}$ cm $^{-{3}}$ offers the highest output power at maximum power added efficiency (PAE) (1.8 W/mm), whereas $3\times 10^{{17}}$ cm $^{-{3}}$ doping provides the highest PAE (>40%). The C-profiles acquired by using secondary ion mass spectroscopy (SIMS), in combination with DCTS, is used to explain the electron trapping effects. Traps associated with the C-doping in the back-barrier are identified and the bias ranges for the trap activation are discussed. The study shows the importance of considering the C-doping level in the back-barrier of microwave GaN HEMTs for power amplification and generation.

Very fast interface traps have recently been suggested to be the main cause behind poor channel-carrier mobility in SiC metal–oxide–semiconductor field effect transistors. It has been hypothesized that the NI traps are defects located inside the SiO2 dielectric with energy levels close to the SiC conduction band edge and the observed conductance spectroscopy signal is a result of electron tunneling to and from these defects. Using aluminum nitride and aluminum oxide as gate dielectrics instead of SiO2, we detect NI traps at these SiC/dielectric interfaces as well. A detailed investigation of the NI trap density and behavior as a function of temperature is presented and discussed. Advanced scanning transmission electron microscopy in combination with electron energy loss spectroscopy reveals no SiO2 at the interfaces. This strongly suggests that the NI traps are related to the surface region of the SiC rather than being a property of the gate dielectric.

This study presents a novel approach to forming low-resistance ohmic contacts for AlGaN/GaN HEMTs. The optimized contacts exhibit an outstanding contact resistance of approximately 0.15 Ω·mm. This is achieved by firstly recessing the barrier of the heterostructure to a depth beyond the channel. In this way, the channel region is exposed on the sidewall of the recess. The coverage of the Ti/Al/Ti ohmic metalization on the sidewall is ensured through tilting of the sample during evaporation. The annealing process is performed at a low temperature of 550 °C. The approach does not require precise control of the recess etching. Furthermore, the method is directly applicable to most barrier designs in terms of thickness and Al-concentration. The impact of recessed sidewall angle, thickness and ratio of Ti and Al layers, and the annealing procedure are investigated. Structural and chemical analyses of the interface between the ohmic contacts and epi-structure indicate the formation of ohmic contacts by the extraction of nitrogen from the epi-structure. The approach is demonstrated on HEMT-structures with two different barrier designs in terms of Al-concentration and barrier thickness. The study demonstrate large process window in regard to recess depth and duration of the annealing as well as high uniformity of the contact resistance across the samples, rendering the approach highly suitable for industrial production processes.