Dong-Joon Shin
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Dong-Joon Shin has a total of 77 co-authors. Here are the top co-authors by number of shared publications:
- Jong-Seon No
Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea
24 shared publications Jong-Seon No
Department of Electrical and Computer Engineering, INMC, Seoul National University, Seoul, South Korea
7 shared publicationsKee-Hoon Kim
Department of Electronic Engineering, Soonchunhyang University, Asan, South Korea
6 shared publicationsHyeong-Gun Joo
5 shared publications- Seunghwan Lee
Hanyang University
5 shared publications - Dae-Woon Lim
Department of Chemistry and Medical Chemistry
4 shared publications
Latest Publications
- 1 September 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Internet of Things Journal
- Vol. 13 (18) , 42881-42896
Hi-SAFE: Hierarchical Secure Aggregation for Lightweight Federated Learning
- 1 September 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Internet of Things Journal
- Vol. 13 (18) , 42881-42896
Hi-SAFE: Hierarchical Secure Aggregation for Lightweight Federated Learning
- Open Access
Hi-SAFE: Hierarchical Secure Aggregation for Lightweight Federated Learning
Federated learning (FL) faces challenges in ensuring both privacy and communication efficiency, particularly in resource-constrained environments such as Internet of Things (IoT) and edge networks. While sign-based methods, such as sign stochastic gradient descent with majority voting (SIGNSGD-MV), offer substantial bandwidth savings, they remain vulnerable to inference attacks due to exposure of gradient signs. Existing secure aggregation techniques are either incompatible with sign-based methods or incur prohibitive overhead. To address these limitations, we propose Hi-SAFE, a lightweight and cryptographically secure aggregation framework for sign-based FL. Our core contribution is the construction of efficient majority vote polynomials for SIGNSGD-MV, derived from Fermat's Little Theorem. This formulation represents the majority vote as a low-degree polynomial over a finite field, enabling secure evaluation that hides intermediate values and reveals only the final result. We further introduce a hierarchical subgrouping strategy that ensures constant multiplicative depth and bounded per-user complexity, independent of the number of users n.
Open AccessHi-SAFE: Hierarchical Secure Aggregation for Lightweight Federated Learning
Federated learning (FL) faces challenges in ensuring both privacy and communication efficiency, particularly in resource-constrained environments such as Internet of Things (IoT) and edge networks. While sign-based methods, such as sign stochastic gradient descent with majority voting (SIGNSGD-MV), offer substantial bandwidth savings, they remain vulnerable to inference attacks due to exposure of gradient signs. Existing secure aggregation techniques are either incompatible with sign-based methods or incur prohibitive overhead. To address these limitations, we propose Hi-SAFE, a lightweight and cryptographically secure aggregation framework for sign-based FL. Our core contribution is the construction of efficient majority vote polynomials for SIGNSGD-MV, derived from Fermat's Little Theorem. This formulation represents the majority vote as a low-degree polynomial over a finite field, enabling secure evaluation that hides intermediate values and reveals only the final result. We further introduce a hierarchical subgrouping strategy that ensures constant multiplicative depth and bounded per-user complexity, independent of the number of users n.
- 18 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Neural Networks and Learning Systems
- Vol. 36 (11) , 19805-19819
FedLSC: Improving Communication Efficiency and Robustness in Federated Learning With Stragglers and Adversaries
Despite significant progress in federated learning (FL), persistent challenges, such as stragglers, adversaries, and communication costs remain. To address these issues, we propose FedLSC, a novel FL framework that leverages layer-selected correlation (LSC) to enhance both robustness and efficiency. In contrast to the existing methods, FedLSC does not rely on public data during model training, making it more practical and resilient in real-world scenarios. FedLSC introduces three key innovations: 1) preprocessing of layer selection (LS), which identifies significant layers to reduce communication costs and performance degradation; 2) local updates using LS-based scaled sign-stochastic gradient descent (SSS), introducing a layer-specific scaling mechanism to mitigate performance loss from quantization and significantly reduce communication costs; and 3) model aggregation via LSC-based schemes, which enhances robustness by processing only the significant layers and mitigating the impact of stragglers and adversaries. Furthermore, integrating the SSS scheme into FedLSC reduces communication costs to as little as 0.01% of those in state-of-the-art (SOTA) method while maintaining performance. Evaluations conducted across various FL scenarios show that FedLSC effectively supports robust performance and efficiency, even in bandwidth-constrained environments, thereby confirming its practicality in modern FL applications.
- 18 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Neural Networks and Learning Systems
- Vol. 36 (11) , 19805-19819
FedLSC: Improving Communication Efficiency and Robustness in Federated Learning With Stragglers and Adversaries
Despite significant progress in federated learning (FL), persistent challenges, such as stragglers, adversaries, and communication costs remain. To address these issues, we propose FedLSC, a novel FL framework that leverages layer-selected correlation (LSC) to enhance both robustness and efficiency. In contrast to the existing methods, FedLSC does not rely on public data during model training, making it more practical and resilient in real-world scenarios. FedLSC introduces three key innovations: 1) preprocessing of layer selection (LS), which identifies significant layers to reduce communication costs and performance degradation; 2) local updates using LS-based scaled sign-stochastic gradient descent (SSS), introducing a layer-specific scaling mechanism to mitigate performance loss from quantization and significantly reduce communication costs; and 3) model aggregation via LSC-based schemes, which enhances robustness by processing only the significant layers and mitigating the impact of stragglers and adversaries. Furthermore, integrating the SSS scheme into FedLSC reduces communication costs to as little as 0.01% of those in state-of-the-art (SOTA) method while maintaining performance. Evaluations conducted across various FL scenarios show that FedLSC effectively supports robust performance and efficiency, even in bandwidth-constrained environments, thereby confirming its practicality in modern FL applications.
- Open Access
- 17 August 2025
- Published by Springer Nature
- p. 105-139
Actively Secure MPC in the Dishonest Majority Setting: Achieving Constant Complexity in Online Communication, Computation Per Gate, Rounds, and Private Input Size
- 17 August 2025
- Published by Springer Nature
- p. 105-139
Open AccessActively Secure MPC in the Dishonest Majority Setting: Achieving Constant Complexity in Online Communication, Computation Per Gate, Rounds, and Private Input Size
- 7 November 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Internet of Things Journal
- Vol. 12 (6) , 7376-7388
Extended Number Theoretic Transform for Lightweight Post-Quantum Cryptosystems in IoT
The primary computational complexity of the lattice-based post-quantum cryptosystems (PQCs), aside from hashing, comes from the polynomial multiplication. Especially, the multiplication efficiency of large-degree polynomials becomes increasingly important for current applications. Therefore, in this article, we propose efficient polynomial multiplication methods, termed as the extended number theoretic transform (NTT), eventually aimed at developing efficient lightweight PQCs suitable for the Internet of Things. The proposed methods utilize the extension of finite fields and an early termination technique to enable efficient NTT implementation using better parameter values. The adoption of arithmetic in the extension field $\mathbb {F}_{q^{m}}$ provides more efficient NTT computation, even when a primitive $2n$ th root of unity, required for NTT, does not exist in the base field $\mathbb {Z}_{q}$ . More importantly, the proposed methods allow for more flexible selection of PQC parameters. Moreover, by using early termination of NTT over the extension field, we further enhance the efficiency of polynomial multiplication. As a result, the proposed methods flexibly select suitable (or smaller) modulus q by optimizing the extension degree m and the incomplete degree l. Finally, we validate the effectiveness of our methods by demonstrating their capability to offer a wide range of parameter values and significantly reduce the size of modulus q. It is confirmed through simulation that the communication efficiency and security are improved by up to 21.43% and 9.09%, respectively. Finally, it is shown that lightweight Crystals-Kyber can be easily constructed by using the proposed methods.
- 7 November 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Internet of Things Journal
- Vol. 12 (6) , 7376-7388
Extended Number Theoretic Transform for Lightweight Post-Quantum Cryptosystems in IoT
The primary computational complexity of the lattice-based post-quantum cryptosystems (PQCs), aside from hashing, comes from the polynomial multiplication. Especially, the multiplication efficiency of large-degree polynomials becomes increasingly important for current applications. Therefore, in this article, we propose efficient polynomial multiplication methods, termed as the extended number theoretic transform (NTT), eventually aimed at developing efficient lightweight PQCs suitable for the Internet of Things. The proposed methods utilize the extension of finite fields and an early termination technique to enable efficient NTT implementation using better parameter values. The adoption of arithmetic in the extension field $\mathbb {F}_{q^{m}}$ provides more efficient NTT computation, even when a primitive $2n$ th root of unity, required for NTT, does not exist in the base field $\mathbb {Z}_{q}$ . More importantly, the proposed methods allow for more flexible selection of PQC parameters. Moreover, by using early termination of NTT over the extension field, we further enhance the efficiency of polynomial multiplication. As a result, the proposed methods flexibly select suitable (or smaller) modulus q by optimizing the extension degree m and the incomplete degree l. Finally, we validate the effectiveness of our methods by demonstrating their capability to offer a wide range of parameter values and significantly reduce the size of modulus q. It is confirmed through simulation that the communication efficiency and security are improved by up to 21.43% and 9.09%, respectively. Finally, it is shown that lightweight Crystals-Kyber can be easily constructed by using the proposed methods.
- Open Access
- 9 January 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 12, 6160-6180
Overflow-Detectable Floating-Point Fully Homomorphic Encryption
A floating-point fully homomorphic encryption (FPFHE) is proposed, which is based on torus fully homomorphic encryption equipped with programmable bootstrapping. Specifically, FPFHE for 32-bit and 64-bit floating-point messages are implemented, the latter showing the state-of-the-art precision among FHEs. Also, a ciphertext is constructed for checking if an overflow has occurred or not while evaluating arithmetic circuits with the proposed FPFHE, which is useful when the message space or arithmetic circuit is too complex to estimate a bound of outputs such as some deep learning applications. Also, homomorphic algorithms, which are crucial components of overflow detectable (OD)-FPFHE, are constructed. First, a state-of-the-art bootstrapping method of TFHE is extended to bootstrap larger messages by using NTT-friendly integer modulus. Second, a subgaussian analysis method is proposed without assuming independent heuristic on AP/GINX-bootstrapping even if the deterministic gadget decomposition is used. Third, the blind rotation algorithm of TFHE is modified such that any secret key having finite non-zero values can be used while keeping the number of NTT operations the same as when the binary key is used. Fourth, various homomorphic algorithms are proposed such as evaluating min and max, lifting a constant message to the monomial exponent, counting the number of consecutive zeros from the most significant in the fraction, and performing carryover after homomorphic operation of floating-point numbers. Finally, 32-bit and 64-bit OD-FPFHEs are implemented and simulation results are provided to confirm that they work well even for extreme cases. Also, it is verified that homomorphic overflow detection is well-operated.
- 9 January 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 12, 6160-6180
Open AccessOverflow-Detectable Floating-Point Fully Homomorphic Encryption
A floating-point fully homomorphic encryption (FPFHE) is proposed, which is based on torus fully homomorphic encryption equipped with programmable bootstrapping. Specifically, FPFHE for 32-bit and 64-bit floating-point messages are implemented, the latter showing the state-of-the-art precision among FHEs. Also, a ciphertext is constructed for checking if an overflow has occurred or not while evaluating arithmetic circuits with the proposed FPFHE, which is useful when the message space or arithmetic circuit is too complex to estimate a bound of outputs such as some deep learning applications. Also, homomorphic algorithms, which are crucial components of overflow detectable (OD)-FPFHE, are constructed. First, a state-of-the-art bootstrapping method of TFHE is extended to bootstrap larger messages by using NTT-friendly integer modulus. Second, a subgaussian analysis method is proposed without assuming independent heuristic on AP/GINX-bootstrapping even if the deterministic gadget decomposition is used. Third, the blind rotation algorithm of TFHE is modified such that any secret key having finite non-zero values can be used while keeping the number of NTT operations the same as when the binary key is used. Fourth, various homomorphic algorithms are proposed such as evaluating min and max, lifting a constant message to the monomial exponent, counting the number of consecutive zeros from the most significant in the fraction, and performing carryover after homomorphic operation of floating-point numbers. Finally, 32-bit and 64-bit OD-FPFHEs are implemented and simulation results are provided to confirm that they work well even for extreme cases. Also, it is verified that homomorphic overflow detection is well-operated.
- Open Access
- 16 November 2023
- Published by Elsevier in ICT Express
- Vol. 10 (3) , 513-518
Effective bi-directional overlapped sliding window decoding of SC-LDPC codes
- 16 November 2023
- Published by Elsevier in ICT Express
- Vol. 10 (3) , 513-518
Open AccessEffective bi-directional overlapped sliding window decoding of SC-LDPC codes
- 3 November 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 3, 421-425
Homomorphic Equal and Less Than Query Protocol
In this paper, we propose a homomorphic protocol in which users can perform privacy-preserving equal query and less than query on a database while concealing both the query val-ues and the query results from the database. This homomor-phic protocol allows for a broader range of query types while preserving privacy, compared to the existing private information retrieval protocol that only allows for querying specific indexes. The proposed homomorphic query protocol based on equal and less than queries can be particularly applied to var-ious scenarios such as querying data produced before certain time.
- 3 November 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 3, 421-425
Homomorphic Equal and Less Than Query Protocol
In this paper, we propose a homomorphic protocol in which users can perform privacy-preserving equal query and less than query on a database while concealing both the query val-ues and the query results from the database. This homomor-phic protocol allows for a broader range of query types while preserving privacy, compared to the existing private information retrieval protocol that only allows for querying specific indexes. The proposed homomorphic query protocol based on equal and less than queries can be particularly applied to var-ious scenarios such as querying data produced before certain time.
- 31 October 2022
- Published by The Korean Institute of Electrical Engineers in The Transactions of The Korean Institute of Electrical Engineers
- Vol. 71 (10) , 1482-1490
A Study on the Assessment Methodology for Climate Change Risk in the Electricity Sector
Natural disasters driven by extreme climate and weather events are probably the types of disasters that mankind has been best adapted to. As the intensity and frequency of events become more serious due to climate change induced by global warming, the stability of the electric power supply and the safety of electrical infrastructures are more threatened. For the sustainable development of human civilization, it is most important to accurately identify hazards in the future environment and to reduce the risks caused by those hazards. However, depending on how these risks are defined and assessed, they may be considered serious or ignored. Therefore, it is necessary not only to identify the hazards well, but also to accurately assess and adapt to the risk of each identified hazard. In this paper, a methodology for assessing and adapting to the risks posed by climate change in the field of electrical installations is presented. The risk assessment methodology will support improving the resilience of the national power grid by enabling efficient use of limited national resources required for climate change adaptation.
- 31 October 2022
- Published by The Korean Institute of Electrical Engineers in The Transactions of The Korean Institute of Electrical Engineers
- Vol. 71 (10) , 1482-1490
A Study on the Assessment Methodology for Climate Change Risk in the Electricity Sector
Natural disasters driven by extreme climate and weather events are probably the types of disasters that mankind has been best adapted to. As the intensity and frequency of events become more serious due to climate change induced by global warming, the stability of the electric power supply and the safety of electrical infrastructures are more threatened. For the sustainable development of human civilization, it is most important to accurately identify hazards in the future environment and to reduce the risks caused by those hazards. However, depending on how these risks are defined and assessed, they may be considered serious or ignored. Therefore, it is necessary not only to identify the hazards well, but also to accurately assess and adapt to the risk of each identified hazard. In this paper, a methodology for assessing and adapting to the risks posed by climate change in the field of electrical installations is presented. The risk assessment methodology will support improving the resilience of the national power grid by enabling efficient use of limited national resources required for climate change adaptation.
- 13 May 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 70 (2) , 736-740
Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems
Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices. To correct errors in one DRAM device, error pattern is determined by even parity bits and error location is determined by the error pattern and cyclic redundancy check (CRC) bits in SDDC decoding. In this brief, a SDDC decoding scheme is proposed, which improves the error-correction performance by uniquely determining the error location. For that purpose, requirements for binary CRC generator polynomials to uniquely determine the error location are derived. Based on these requirements, a systematic method for constructing CRC generator polynomials is proposed, which guarantees 100% error-correction rate. Finally, it is confirmed that the proposed SDDC decoding scheme has lower decoding complexity compared with various ECC schemes and also shows 100% SDDC decoding success through simulation.
- 13 May 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 70 (2) , 736-740
Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems
Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices. To correct errors in one DRAM device, error pattern is determined by even parity bits and error location is determined by the error pattern and cyclic redundancy check (CRC) bits in SDDC decoding. In this brief, a SDDC decoding scheme is proposed, which improves the error-correction performance by uniquely determining the error location. For that purpose, requirements for binary CRC generator polynomials to uniquely determine the error location are derived. Based on these requirements, a systematic method for constructing CRC generator polynomials is proposed, which guarantees 100% error-correction rate. Finally, it is confirmed that the proposed SDDC decoding scheme has lower decoding complexity compared with various ECC schemes and also shows 100% SDDC decoding success through simulation.