Ilya Besedin

Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded Z Z logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.

Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state—a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two 3-qubit modules on a single carrier chip, with connectivity for intra- and intermodule entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an intermodule two-qubit gate enables subexponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of 4 for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.

When using unitary gate sequences, the growth in depth of many quantum circuits with output size poses significant obstacles to practical quantum computation. The quantum fan-out operation, which reduces the circuit depth of quantum algorithms such as the quantum Fourier transform and Shor’s algorithm, is an example that can be realized in constant depth independent of the output size. Here, we demonstrate a quantum fan-out gate with real-time feedforward on up to four output qubits using a superconducting quantum processor. By performing quantum state tomography on the output states, we benchmark our gate with input states spanning the entire Bloch sphere. We decompose the output-state error into a set of independently characterized error contributions. We extrapolate our constant-depth circuit to offer a scaling advantage compared to the unitary fan-out sequence beyond 25 output qubits with feedforward control, or beyond 17 output qubits if the classical feedforward latency is negligible. Our work highlights the potential of midcircuit measurements combined with real-time conditional operations to improve the efficiency of complex quantum algorithms.

Superconducting fluxonium qubits provide a promising alternative to transmons on the path toward large-scale superconductor-based quantum computing due to their better coherence and larger anharmonicity. A major challenge for multi-qubit fluxonium devices is the experimental demonstration of a scalable crosstalk-free multi-qubit architecture with high-fidelity single-qubit and two-qubit gates, single-shot readout, and state initialization. Here, we present a two-qubit fluxonium-based quantum processor with a tunable coupler element. We experimentally demonstrate fSim-type and controlled-Z-gates with 99.55 and 99.23% fidelities, respectively. The residual ZZ interaction is suppressed down to the few kHz levels. Using a galvanically coupled flux control line, we implement high-fidelity single-qubit gates and ground state initialization with a single arbitrary waveform generator channel per qubit.

Experimental realization of stabilizer-based quantum error correction (QEC) codes that would yield superior logical qubit performance is one of the formidable task for state-of-the-art quantum processors. A major obstacle toward realizing this goal is the large footprint of QEC codes, even those with a small distance. We propose a circuit based on the minimal distance-3 QEC code, which requires only five data qubits and five ancilla qubits, connected in a ring with iswap gates implemented between neighboring qubits. Using a density-matrix simulation, we show that, thanks to its smaller footprint, the proposed code has a lower logical error rate than surface-17 for similar physical error rates. We also estimate the performance of a neural-network-based error decoder, which can be trained to accommodate the error statistics of a specific quantum processor by training on experimental data.

A superconducting fluxonium circuit is an RF-superconducting quantum interference device-type flux qubit that uses a large inductance built from an array of Josephson junctions or a high kinetic inductance material. This inductance suppresses charge sensitivity exponentially and flux sensitivity quadratically. In contrast to the transmon qubit, the anharmonicity of fluxonium can be large and positive, allowing for better separation between the low energy qubit manifold of the circuit and higher-lying excited states. Here, we propose a tunable coupling scheme for implementing two-qubit gates on fixed-frequency fluxonium qubits, biased at half flux quantum. In this system, both qubits and couplers are coupled capacitively and implemented as fluxonium circuits with an additional harmonic mode. We investigate the performance of the scheme by simulating a universal two-qubit fSim gate. In the proposed approach, we rely on a planar on-chip architecture for the whole device. Our design is compatible with existing hardware for transmon-based devices with the additional advantage of lower qubit frequency facilitating high-precision gating.

The superconducting fluxonium circuit is an RF-SQUID-type flux qubit that uses a large inductance built from an array of Josephson junctions or a high kinetic inductance material. This inductance suppresses charge sensitivity exponentially and flux sensitivity quadratically. In contrast to the transmon qubit, the anharmonicity of fluxonium can be large and positive, allowing for better separation between the low energy qubit manifold of the circuit and higher-lying excited states. Here, we propose a tunable coupling scheme for implementing two-qubit gates on fixed-frequency fluxonium qubits, biased at half flux quantum. In this system, both qubits and coupler are coupled capacitively and implemented as fluxonium circuits with an additional harmonic mode. We investigate the performance of the scheme by simulating a universal two-qubit fSim gate. In the proposed approach, we rely on a planar on-chip architecture for the whole device. Our design is compatible with existing hardware for transmon-based devices, with the additional advantage of lower qubit frequency facilitating high-precision gating.