Axel Jantsch

The efficient deployment of deep neural networks (DNNs) on resource-constrained edge devices necessitates a delicate balance between model accuracy, communication bandwidth, and computational latency. While existing methods often address partitioning, quantization, or compression in isolation, this paper introduces CO-NAS (Joint Neural Architecture Search for Compression, Quantization, and Edge–Cloud Model Offloading), a unified framework that jointly optimizes these three critical dimensions for collaborative edge-cloud inference. By utilizing an adapted version of the stochastic architecture search (SNAS) paradigm, CO-NAS leverages Temperature-Annealed Softmax relaxations to enable gradient-based optimization over discrete choices of partition points, compression ratios, and activation bit-widths. Extensive experiments on ResNet-50 and VGG-16 across CIFAR-100 and Fashion-MNIST datasets demonstrate the framework’s efficacy. CO-NAS discovers Pareto-optimal configurations, such as a ResNet-50 model for CIFAR-100 achieving 70.1% accuracy with extreme compression (48× channel reduction and 1-bit quantization), representing a total compression of over 1500× on transmitted features. Crucially, exhaustive grid search validation confirms that CO-NAS reliably identifies top-performing architectures within the vast search space, while achieving a 21×-27× reduction in search cost compared to the exhaustive baseline. The results validate CO-NAS as a scalable and efficient approach for automating the co-design of accurate and communication-efficient neural networks for the edge-cloud paradigm.

Condition Monitoring of devices and control systems allows for a decrease in maintenance costs while requiring less computational effort than machine learning methods. To provide the option to include a monitoring circuit on a sensor or small edge device, and thus further lower computational and communication overhead, this work presents a minimized hardware implementation of a condition monitoring algorithm called TCAM and compares it to a more traditional implementation of the algorithm. Furthermore, a trade-off analysis examines the effect of sample bit widths on gate count and accuracy. For the selected case study, the gate count has been decreased by 57 % and the needed memory size by roughly 86 % while still yielding system state detection results at the same level of accuracy. For an example hydraulic monitoring application with four input signals monitored and a 9 bit numeric representation delivering reasonable accuracy, TCAM can be implemented with 1918 logic gates and 3092 bit RAM.

Bearing fault detection is critical for ensuring the reliability of industrial machinery, as mechanical failures can lead to significant downtime and maintenance costs. This paper presents a hardware-efficient accelerator for bearing fault detection based on Support Vector Machines (SVMs). Unlike neural network–based accelerators, which are often over-parameterized and demand substantial hardware resources, the proposed design focuses on compactness and hardware efficiency. By combining carefully selected time-domain features with quantization and normalization techniques, we developed a hardware-efficient architecture suitable for both FPGA and ASIC implementation. Evaluated on the Case Western Reserve University (CWRU) bearing dataset, the accelerator achieves 96.93% accuracy in the single-variate and 98.42% in the multi-variates implementation. The FPGA implementation and the ASIC synthesized in TSMC 65-nm demonstrate significantly lower hardware requirements compared to state-of-the-art designs, making the proposed approach highly suitable for deployment in resource-constrained environments.

Deploying deep neural networks (DNNs) in real-time, resource-constrained edge environments remains a significant challenge due to the increasing depth and computational demand of state-of-the-art models. While state-of-the-art split computing and early-exit architectures independently offer solutions to reduce inference latency and offloading overhead, they are rarely integrated in a unified framework. This paper introduces BranchySplit, a novel architecture that combines dynamic state-of-the-art split computing with early exit mechanisms to accelerate inference in edge-cloud systems. Our method employs a shared dynamic autoencoder to support multiple partitioning points, enabling runtime adaptability based on varying system conditions. By integrating early exit branches at intermediate layers, the model can terminate inference early when confidence is sufficient, further reducing computation and communication. Extensive experiments on Caltech-256 and Tiny-ImageNet dataset using four backbone models (VGG-16, ResNet-50, Efficientformerv2-S2, and ConvNeXT-small) show that our approach consistently outperforms the traditional split computing approaches, achieving up to 2.7x latency speed-up compared to an all-in-server solution, while maintaining comparable or even improved accuracy. In addition, our proposed dynamic compression pipeline achieves a higher speed-up compared to the pipeline in similar work, i.e. SPINN, with up to 10x for ResNet50 on caltech-256. These results demonstrate the efficacy of BranchySplit in enabling low-latency, resource-efficient vision inference in heterogeneous edge-cloud settings.