Hyungtak Kim

A novel enhancement-mode (E-mode) p-GaN/AlGaN/GaN high-electron-mobility transistor (HEMT) featuring a diode-engineered gate configuration was developed to extend the gate voltage swing range. In the proposed design, a small diode is monolithically integrated in series to the p-GaN gate, introducing an additional forward voltage drop to the threshold voltage of the HEMT. This approach significantly increases both the threshold voltage and the maximum allowable gate voltage swing compared to conventional p-GaN gate HEMTs, which typically exhibit low threshold voltages and limited gate swing ranges. The device employs a standard heterostructure, and the compact size of the embedded diode ensures that the increase in chip area is negligible.

This study reports the fabrication and characterization of a p-GaN/AlGaN/GaN heterostructure field-effect transistor (HFET) incorporating a boron nitride (BN) film. The BN film was deposited at room temperature via RF sputtering (RT-RF sputtering) onto a SiOx. passivation layer. A dual-layer passivation scheme–comprising the SiO. layer and the room-temperature-deposited BN film–was proposed to enhance interface quality and improve the on-resistance characteristics. The RT-RF sputtering BN film was found to increase the 2DEG density at the AlGaN/GaN interface without degrading the overall device performance. As a result, the on-resistance was reduced by 30%.

The effect of temperature on gate degradation behavior was analyzed in Schottky-type p-GaN gate HEMTs under a positive gate voltage. TDDB measurements were conducted at various temperatures, revealing an accelerated gate failure rate at lower temperatures. A Weibull distribution analysis was employed to predict the 10-year rated gate voltage, showing that the rated voltage at −10 °C is significantly lower than at 60 °C. Furthermore, the derived activation energy of −0.22 eV indicates that gate degradation intensifies in colder environments. Hole accumulation occurring at the p-GaN/AlGaN interface can promote degradation by facilitating electron injection and accelerating defect generation in the presence of strong electric fields. At higher temperatures, hole release mitigates charge accumulation, thereby extending device longevity. These findings highlight the necessity of reliability assessments for p-GaN gate HEMTs suitable for environments with low temperatures, including space and polar environments.

In this work, we analyzed the effects of hot carrier injection in short-channel AlGaN/GaN high electron mobility transistors by identifying hot carrier stress conditions using electroluminescence (EL) spectroscopy. After applying hot carrier stress, degradation of the device parameters was observed. This degradation worsened under conditions of peak EL signal intensity (VG = -3 V, VD = 40 V), which accelerated the generation of hot carriers. However, when the devices were subjected to on-state stress while maintaining the same power consumption as in hot carrier stress conditions, almost no degradation was detected. This suggests that the primary cause of degradation under hot carrier stress conditions is the continuous generation of hot carriers, which is accelerated by a high electric field. This further demonstrates the feasibility of using EL spectroscopy to identify conditions for the accelerated degradation of device parameters caused by hot carriers.

In this work, we investigated the instability of threshold voltage (Vth) in p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) under positive gate biases and high temperatures. We reveal an abnormal temperature dependence of threshold voltage instability, suggesting that threshold voltage instability significant differences at elevated temperatures and is primarily attributed to the trapping/de-trapping of charged carriers. Notably, the positive shift in threshold voltage diminished and eventually reversed at low gate bias as the temperature increased. In contrast, the negative shift intensified with increasing temperature but began to mitigate above 100 ° C at high gate bias due to an enhanced de-trapping process of electrons and holes. These results suggest the presence of multiple mechanisms behind the threshold voltage instability under varying thermal conditions.

In this study, we proposed a novel p-GaN/p-AlGaN/AlGaN/GaN heterojunction field-effect transistor (HFET). When a selective etching process is used to precisely etch the p-GaN layer of a conventional p-GaN/AlGaN/GaN HFET structure, over-etching-induced surface damage can degrade the device characteristics. By inserting a p-AlGaN layer between p-GaN and AlGaN, the over-etching-induced plasma damage at the surface of the p-AlGaN layer can subsequently be removed using a low-damage atomic layer etching process. As a result, the surface damage issue can be mitigated. An additional benefit of using the p-AlGaN layer is a higher threshold voltage. The fabricated p-GaN/p-AlGaN/AlGaN/GaN HFET exhibited a remarkably high threshold voltage of 6 V with a specific on-resistance of 7.47 $\text{m}\cdot \Omega $ cm2.

In this study, we conducted an optimization of a low-damage selective etching process utilizing inductively coupled plasma-reactive ion etch (ICP-RIE) with a fluorine-based gas mixture. This optimization was carried out for the fabrication of p-GaN gated AlGaN/GaN enhancement-mode (E-mode) heterojunction field-effect transistors (HFETs). The optimum process conditions resulted in an etch selectivity of 21:1 (=p-GaN:Al_0.2Ga_0.8N) with a p-GaN etch rate of 5.2 nm/min and an AlGaN etch rate of 0.25 nm/min. In comparison with an oxygen-based selective etching process, the fluorine-based selective etching process demonstrated reduced damage to the etched surface. This was confirmed through current–voltage characteristics and surface roughness inspections. The p-GaN gated AlGaN/GaN E-mode device, fabricated using the optimized fluorine-based selective etching process, achieved a high threshold voltage of 3.5 V with a specific on-resistance of 5.3 mΩ.cm² for the device and with a gate-to-p-GaN gate distance of 3 μm, a p-GaN gate length of 4 μm, and a p-GaN gate-to-drain distance of 12 μm. The catastrophic breakdown voltage exceeded 1350 V.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (V_TH) depended on the range of the gate stress voltage (V_G.stress) at room temperature. However, the positive shift of V_TH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of V_TH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (I_GD and I_GS) before and after the stress test. The difference between the gate–source current and the gate–drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.