Rüdiger Quay

Decomposition of novel Sc precursors for MOCVD are studied by density functional theory and evaluated by examining AlScN/GaN heterostructures for high-electron mobility transistors.

Semi-insulating GaN layers for high-electron mobility transistors (HEMTs) used in radio frequency applications are typically achieved through Fe-doping, despite its known adverse effects on transport properties. In this paper, we investigate the possibility of using Mn as an alternative dopant to Fe for GaN buffer layers grown by metal-organic chemical vapor deposition and assess its incorporation onto the subsequent non-intentionally doped (nid) layers. For this purpose, two studies were conducted: first, epitaxial heterostructures for HEMTs were grown with varying the thickness of the nid GaN layer, while keeping the total GaN stack thickness and the Mn-doping level, followed by varying the Mn-doping level and keeping the GaN stack thickness. The Mn-doped buffer layers showed a much faster concentration decay into the subsequent nid GaN layers than Fe. The samples maintained good surface morphology and crystalline quality, and their transport properties did not degrade with different GaN stack thicknesses and doping levels, showcasing Mn as a promising dopant for semi-insulating GaN buffer layers.

This study examines the impact of humidity and temperature on the reliability of silicon nitride (SiN) passivated 80 μm gallium nitride (GaN) metal–insulator–semiconductor high-electron mobility transistor (HEMT) test structures. Degradation is determined by threshold voltage shifts in the capacitance–voltage C(V) characteristics. High temperature and humidity, while maintaining a constant gate and drain bias, are deleterious to reliability, leading to pronounced positive threshold voltage shifts (ΔVth). In contrast to previous humidity studies on Schottky-gate GaN HEMTs, which reported negligible humidity-induced threshold shifts, the present work shows that GaN MISHEMTs exhibit a strong sensitivity of ΔVth to humidity. A lifetime analysis based on Peck’s model was conducted to quantify these effects, yielding a humidity acceleration factor B = 0.021 at 85 °C and an activation energy Ea = 0.45 eV in ambient air. It has been shown that increasing the relative humidity (RH) from 0% to 40% reduces the time to failure by approximately one order of magnitude. A comparison of different SiN passivation thicknesses reveals that thick gate passivation substantially mitigates humidity-induced degradation. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) analysis showed that degradation mainly occurs in the access region rather than the intrinsic region. The presence of oxidized SiN passivation and cracks was revealed by both ToF-SIMS and scanning electron microscopy/element-dispersive x-ray analysis of these regions. The epitaxial layers and the SiN passivation are identical to those of short-channel (100 nm) GaN HEMTs, meaning that these findings can be transferred.

In this letter, we present a D-band power amplifier (PA) monolithic microwave integrated circuit (MMIC), manufactured in a gallium nitride (GaN)-on-silicon carbide (SiC) high electron-mobility transistor (HEMT) technology. The PA comprises six stages of 70-nm gate-length HEMTs and features 4-way corporate power combining, which results in an output stage gate-width of 352 $\mu $ m. We develop and analyze a loss-optimized interstage matching network (ISMN) topology, which is crucial for driving the output stage. As a result, the PA delivers a saturated output power (P _sat) of more than $\mathrm {25.2~dBm }$ between 125 and 151 GHz, and a peak P _sat of $\mathrm {28~dBm }$ at the center of the frequency band. The high P _sat and a small chip size (3.125 mm²) translate into a power density (P_dens ) of more than 0.2 W/mm². To the best of our knowledge, this PA MMIC demonstrates the highest P _sat and P_dens beyond 120 GHz across all technologies.

This article presents the design and modeling of two distributed resistive downconverter monolithic microwave integrated circuits (MMICs), realized in 100- and 70-nm AlGaN/GaN high-electron-mobility transistor (HEMT) technologies operating up to D-band frequencies (110–170 GHz). A dedicated transistor model that describes both the 100-nm and the scaled 70-nm HEMTs has been developed and extracted and has been used for the design of high-frequency mixers. The model is based on the physics-based advanced SPICE model for GaN HEMTs (ASM-HEMT). The standard ASM-HEMT model has been adopted by including a more precise model of the influence of velocity saturation and channel-length modulation (CLM) for both drain current and intrinsic capacitances and a cross-coupling (CC) capacitances model, to improve low-voltage mixer simulations up to at least D-band frequencies. The proposed MMICs can be operated either in a drain-pumped or gate-pumped mode. At 9 dBm of local oscillator (LO) power and a fixed intermediate frequency (IF) of 200 MHz, the 70- and 100-nm gate-length drain-pumped MMICs have an average conversion gain (CG) of −8.7 dB and −9.3 dB over a wide radio frequency (RF) band of 50–150 GHz, respectively. In gate-pumped operation, the CG is approximately 2 dB lower. The 100-nm HEMT MMIC has an RF input power related −1-dB compression point ( $P_{\mathrm {-1\text {dB}}}$ ) of 3 dBm in the drain-pumped mode and the $P_{\mathrm {-1\text {dB}}}$ increases to 9 dBm in gate-pumped operation. The 70-nm HEMT MMIC, in comparison, achieves a $P_{\mathrm {-1\text {dB}}}$ of 2 and 10 dBm for drain and gate LO-driven operations, respectively.

Diabetes, projected to affect over 1.3 billion people by 2050, presents significant healthcare burdens and environmental challenges, necessitating innovative and sustainable solutions to manage complications effectively. This study applies life cycle assessment to evaluate the environmental impacts of two semiconductor-enabled diabetes care devices: (1) a single-use urine-based C-peptide measurement strip aligned with the reduce strategy and (2) a reusable smart wound dressing for chronic wound monitoring under the reuse strategy. Integrating green electricity reduced the total lifecycle global warming potential by 16.2% for the urine strip and 0.4% for the smart wound dressing. The results emphasize the importance of tailored design strategies, showing that the impact of green integrated circuits is substantial for single-use reduce systems, while long-term treatments benefit more from reuse strategies paired with durable, complex designs that extend component lifespan and limit new manufacturing burdens.

In this article, the monolithic integration of an adaptive local oscillator (LO) leakage cancellation circuit together with an unbalanced resistive in-phase and quadrature (IQ) high-electron-mobility transistor (HEMT) mixer is presented. The proposed calibration algorithm for the cancellation signal is tolerant against any nonideal component responses. A typical LO-to-radio frequency (RF) isolation of 60 dB is achieved, which corresponds to a LO leakage of −55 dBm at saturated mixer operation. To the best of the authors’ knowledge, this is the highest reported performance of a monolithic approach beyond 100 GHz. As part of this work, the leakage cancellation’s sensitivity with regard to environmental changes is investigated. Furthermore, a semi-balanced IQ mixer is implemented in the same technology. An analytic equation for its LO suppression as a function of amplitude and phase imbalance is derived. Detailed comparisons of the output spectra of both mixers, their two-tone intermodulation distortion characteristics, and noise figures (NFs) complement this study.

We present enhancement- and depletion-mode digital logic gates and circuits with back-gate biasing in a Four-pole high-electron-mobility transistor on Silicon technology. This work uses a 20-nm gate-length InGaAs HEMT-on-Si with the option to place an electron-beam-lithography defined back-gate below the InGaAs channel by wafer bonding. By applying back-gate bias, the threshold voltage is modulated to convert normally depletion-mode devices into enhancement-mode devices, without altering the physical structure or processing steps. The back-gated RF transistors are used directly to implement digital logic gates such as NOT, NAND, and NOR, as well as a D-LATCH circuit, and are demonstrated using the E/D logic approach. Additionally, the effect of back-gate biasing on the power consumption of logic gates is analyzed. The proposed circuits provide the opportunity to integrate logic components with state-of-the-art RF circuits monolithically.