Atsuo Kawamura

This paper is a re-evaluation of a completed project (High Efficiency Demonstration Grant Using High Voltage SiC Device) from the perspective of accurate efficiency measurement; additionally, this paper discusses on device dv/dt estimation. A topology called the high-efficiency energy conversion system (HEECS), which is one variety of partial boost circuit topologies, is introduced to achieve efficiency over 99.5%. The topology exhibits a very high efficiency for applications in which the output voltage variation is within a certain ratio of the rated output voltage. This paper summarizes the basic features of the topology and theoretically derives the principle of high-efficiency realization. The high efficiency is measured by the back-to-back(BTB) connection of two converters, and the efficiency and accuracy on this method are theoretically derived and confirmed using the measured data of 3.3 kV output voltage at 100 kW output. The theoretical estimation of dv/dt for a 3.3 kV SiC device to reduce dual-active-bridge(DAB) soft-switching loss is discussed. Furthermore, a trend of DC-DC conversion efficiency is shown, and we show that the partial boost topology is a promising approach for achieving high efficiency dc-dc conversion.

A single-phase grid-connected inverter with an unfolding circuit typically consists of a first-stage dc/dc converter, which generates fully rectified sinusoidal waveforms, and a second-stage unfolding inverter, which switches every 180° of the line frequency waveform. This converter exhibits low switching loss and high efficiency, and the operating principle of the unfolding inverter typically includes synchronous voltage and current. However, limited studies have focused on the operation of inverters with power factor (PF) less than unity. Such operations often result in large overshoots and oscillations in the output voltages. To address this problem, we proposed a novel control scheme that enables leading PF operation without additional circuitry and overcomes the aforementioned limitations in the previous literature. Thus, this paper describes a novel control scheme that enables lagging PF operation. Notably, for a lagging PF, a phenomenon in which the dc voltage inevitably increases immediately after unfolding is known to occur, and herein, this phenomenon is used in reverse to rapidly decrease the dc current. Consequently, we develop a method to land the circuit variables at normal mode steady-state value by using reverse-polarity pulse width modulation (PWM)/forward-polarity PWM combination of the unfolding inverter and a virtual PWM inverter in the proposed controller. The control method is validated using simulations and experiments, and it is found to facilitate the four-quadrant operation of the unfolding inverter.

A single-phase grid-connected inverter with an unfolding circuit consists of a first-stage dc/dc converter, which generates fully rectified sinusoidal waveforms, and a second-stage unfolding inverter, which switches every 180° of line frequency waveform. This converter exhibits low switching loss and high efficiency. Digitally controlled unfolding inverters can be used in numerous applications, such as power supplies to resistive loads and single-phase grid-connected inverters. The operating principle of an unfolding inverter is typically synchronous voltage and current. However, a reactive power supply function with a leading power factor (pf) (lagging pf from the grid perspective) is typically required for grid-connected inverters to suppress the terminal overvoltage. Limited studies have been focused on the operation of inverters with pf less than unity. Such an operation results in large overshoot and oscillation in the output voltage because of the difficulty in coping with large current fluctuations after voltage zero crossing. To this end, we propose a novel control scheme that enables leading pf operation without additional circuitry and overcomes the aforementioned limitations. When the unfolding inverter is operated with leading pf, a special mode called “all-conduction mode” occurs after voltage zero crossing. The proposed scheme implements appropriate dc current control to terminate this mode, resulting in a smooth transition to the normal mode steady state with pf less than unity. The scheme verifiably showcases exceptional efficiency in the conducted simulations and experiments.

Battery-equipped apparatuses, such as electric vehicles (EVs), renewable energy generations, and mobile devices, are widely used and still being developed. For the design and evaluation of these devices, there is a growing demand for dc power supplies to test the charge-discharge characteristics and lifetimes of batteries. As the voltage and performance of the batteries increase, the power supplies for the battery test must be able to handle higher voltages and have a faster output transient response. To handle a high voltage, multilevel converters that use multiple power devices with lower voltage ratings have often been used in recent years, in addition to using a single power device with high-voltage ratings. Among various circuit topologies, modular multilevel converters (MMCs) have been actively studied and developed. However, unlike dc-ac and ac-dc conversions, dc-dc conversion in MMCs has a problem in that the cell capacitor voltages cannot be balanced in principle because of less redundancy of operation states. Therefore, most MMC-based dc-dc converters achieve voltage balancing control by combining a dc-ac conversion, isolation transformer or inductor, and ac-dc conversion. However, these circuit configurations tend to have a large equivalent inductance and are unsuitable for achieving a fast output response. In this study, we analyze the dc-dc operation and its problems in the MMC circuit. Based on the analysis, a circuit topology using auxiliary inductor circuits and a control method suitable for a dc-dc converter are proposed. A prototype of a 6-cell MMC-based dc-dc converter using SiC-MOSFETs was designed and implemented, and it was demonstrated that cell voltage balancing control and fast output response could be realized.

Electrical power converters use semiconductor switching devices for a larger loss reduction compared with non-switching power linear amplifiers, such as class-B amplifiers. However, it is well known that the switching operation produces harmonics and electromagnetic interference noise; consequently, passive components are usually required for the suppression of these harmful subproducts. The use of recent fast power devices such as silicon carbide and gallium nitride devices produces larger dv / dt and di / dt than Si power devices, and, as a result, the above-mentioned problem becomes more tangible. In this study, we propose the concept of a family of multilevel linear amplifiers (MLLA) in which no switching power conversion is possible. MLLAs consist of series-connected switching devices, and only one of them operates as a linear amplifier, and the loss is much less than that of the class-B amplifier. The concept of the family is very useful when a proper MLLA topology is selected for application. In this study, three types of MLLA—diode-clamped, flying-capacitor, and novel modular-cascaded linear amplifiers—with four devices connected in series were investigated, and an efficiency of >82% was demonstrated in the experiments.

A DC-AC conversion efficiency of over 99.7% is experimentally measured using a two battery high efficiency energy conversion system (HEECS) inverter. The accuracy of the efficiency measurement is evaluated by two methods: the direct measurement method and the loss breakdown method. After several measurements, calculations and analyses it is concluded that the measurement error based on the loss breakdown method is 0.04%.

This paper presents a flying-capacitor linear amplifier (FCLA) that achieves high efficiency, low harmonic distortion, and low electromagnetic interference (EMI). A conventional class-B linear amplifier cannot be used in power conversion applications, because the power loss generated in active-state MOSFETs is high compared with the loss generated in switching operations. In the proposed FCLA, multiple series-connected MOSFETs are used, and only one MOSFET operates in the active state at a time. Thus, the power loss generated in the MOSFETs can be reduced, and the FCLA can achieve high efficiency without performing the switching operation. In this study, the features of the FCLA and conventional linear amplifiers are theoretically compared and evaluated. Moreover, a voltage balancing control for flying capacitors is proposed and verified through simulations and experiments. It is demonstrated that the prototype 12-series FCLA achieves over 89% efficiency and generates low harmonics and low EMI. The proposed configuration is useful for increasing the number of series MOSFETs, and it contributes to realizing a power converter with advantages such as low harmonic distortion, low EMI, and high efficiency.

In recent years, pulse operation function has been increasingly used in both the film formation and semiconductor manufacturing processes. As the one of the pulse operations, high/low pulse operation has also attracted considerable attention. To perform a high/low pulse operation by using the DC/DC converter, we require fast control responses of the DC/DC converter. Therefore, we applied the three-phase interleave of the circuit and deadbeat control. In our previous study, we derived the control equation of the deadbeat control by considering the delay time. We determined the manipulated value of the reference phase by the control equation, however, the other phases were decided by shifting the manipulated value of the reference phase. In this study, we determine the manipulated value of each phase, showing transition time of 7.0 μs for the high/low pulse operation of 280 V/70 V.