Masoud Babaie

Superconducting nanowire single-photon detectors (SNSPDs) have emerged as leading cryogenic photon detectors, thanks to their high detection efficiency and low jitter. However, their large-scale integration remains limited by the wiring bottleneck between the cryogenic detectors and their room-temperature readout electronics. In applications such as color-center-based quantum computers (QCs), thousands of detectors may need to operate in parallel within a limited cryogenic cooling budget, thus asking for a scalable, low-power cryogenic electronic readout. To address these needs, this work introduces a cryogenic readout circuit directly wire-bonded to the SNSPD and using a high-impedance input to maximize the quality of the detector signal, thus relaxing the requirement of the cascaded amplifier and reducing its power consumption. An active quenching circuit is then adopted to ensure a reliable reset after the latching of the detector induced by such high input impedance. Implemented in 40-nm CMOS with an active area of 2, the system achieves competitive performance at 0.1 K, delivering low timing jitter (<40 ps), high speed (dead time of ≈5 ns), and dark count rates (DCRs) below 1 Hz, while achieving a 5× reduction in power consumption (down to 20 μW) with respect to the cryogenic-readout state-of-the-art. Its ultralow-power operation and compact footprint make the proposed solution well-suited for integration within large-scale quantum-computing architectures.

Semiconductor-based cryogenic quantum processors require the accurate biasing of a large number of gate electrodes, which are typically individually wired to room-temperature DACs. To prevent the wiring bottleneck when scaling to future very large processors, this work proposes a scalable cryo-CMOS DAC that can operate with a S&H demultiplexer close to the quantum processor. By adopting an integrator-based switched-capacitor DAC with a dynamically-biased high-voltage output stage, both the required large output range and high resolution can be achieved while sharing the DAC over a large number of electrodes, thus improving the power efficiency. Fabricated in a 22-nm FinFET technology, the DAC occupies 0.076 mm². At 4.2 K (RT), it achieves an LSB of $57.1~\mu $ V ( $68.3~\mu $ V) over a 3 V range with $188~\mu $ V_rms ( $192~\mu $ V_rms) noise and 36.5-LSB (12.6-LSB) INL while dissipating $157~\mu $ W ( $138~\mu $ W). The low power dissipation and the potential to drive more than 30,000 electrodes paves the way for scalable biasing of quantum processors operating down to mK temperatures.

This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5K. By adopting sensing elements (CMOS bulk diodes, PMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order Sigma-Delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73K (4 samples, 2-point trim), a resolution below 0.05K for a 102.4ms readout duration, and a power consumption of 15.5μW (93.5μW) at 5K (296K).

The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of DC bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this paper presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryo-CMOS demultiplexer and a cryo-CMOS DC DAC have been developed in a 22-nm FinFET process to control a co-developed 2D-array designed with 648 Single Hole Transistors (SHTs). Thanks to the dissipation below 120 $\mu$W, the whole system operates at temperatures below 70mK in a custom-built electrical/mechanical infrastructure embedded in a standard singlepulse- tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold (S/H) structures, allowing to store 96 unique bias voltages over a 3V range with a voltage drift between 60 $\mu$V/s and 18 mV/s. This work demonstrates a tight integration at mK-temperatures of cryo- CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors towards the large number of qubits required for a practical quantum computer.

This article presents a sub-7-GHz receiver (RX) for the fifth-generation (5G) local area base station applications. A Rauch transimpedance amplifier (TIA) with a third-order high-pass impedance in its feedback is adopted to enhance RX selectivity and provide higher loop gain (LG) at the bandwidth edge, improving in-band linearity for high-bandwidth applications. An N-path notch filter, sharing switches with down-converting passive mixers, is incorporated in the low-noise transconductance amplifier (LNTA) to enhance out-of-band linearity without limiting the RX’s operating frequency. Additionally, a frequency-dependent negative capacitance is realized at the LNTA input by exploiting the bandpass characteristic of the TIA input impedance, which helps achieve a flat in-band response, extend the RX bandwidth, and improve front-end filtering roll-off. Fabricated in 40-nm CMOS technology, the RX occupies a 1.3-mm² area, operates from 0.4 to 7.3 GHz, and consumes 105–195 mW from a 1.3-V supply. It achieves a third-order output third-order intercept point (OIP3) of 27–38 dBm over a 300-MHz channel bandwidth and a noise figure (NF) of 3.2–5.8 dB across its operating range. With its high linearity, low NF, and enhanced selectivity, the RX satisfies 3GPP standard requirements for reference sensitivity, in-band blocking, close-in blocking, and far-out blocking.

Spins associated to solid-state color centers are a promising platform for investigating quantum computation and quantum networks. Recent experiments have demonstrated multiqubit quantum processors, optical interconnects, and basic quantum error-correction protocols. One of the key open challenges towards larger-scale systems is to realize high-fidelity universal quantum gates. In this work, we design and demonstrate a complete high-fidelity gate set for the two-qubit system formed by the electron and nuclear spin of a nitrogen-vacancy center in diamond. We use gate set tomography (GST) to systematically optimize the gates and demonstrate single-qubit gate fidelities of up to 99.999 ( 1 ) % and a two-qubit gate fidelity of 99.93 ( 5 ) % . Our gates are designed to decouple unwanted interactions and can be extended to other electron-nuclear spin systems. The high fidelities demonstrated provide opportunities towards larger-scale quantum processing with color-center qubits.