Riccardo Zese

In this paper, we present a detailed comparative analysis of two 3-bit quantizer models suitable for low bit-width quantization: the Power-of-Two Level Quantizer (PoTLQ) and the Integer 3 Quantizer (INT3). PoTLQ is a symmetric, non-uniform quantizer whose positive representation levels double successively, enabling a compact and hardware-friendly implementation. INT3, on the other hand, is a symmetric, uniform quantizer with integer-valued representation levels. While both quantizers offer simplicity in design and ease of implementation, the robustness of their performance to changes in input data variance remains insufficiently explored. In this paper, we therefore conduct a theoretical and numerical analysis of the performance of both quantizer models by comparing their signal-to-quantization noise ratio (SQNR) behavior under varying input variances. The analysis provides insights into achieving a trade-off between non-uniform and uniform quantization in low bit-width scenarios, offering guidance on quantizer selection based on input variance dynamic.

Recent advancements in neural network (NN) hardware and software have introduced 8-bit Floating-Point (FP8) format as promising candidate for reducing memory usage and computational overhead. This article investigates the potential for further compressing FP8) data by applying Golomb-Rice (GR) coding. In the FP8 format, the 8 bits are allocated to represent the sign, exponent and mantissa using natural binary encoding. To achieve efficient compression, the GR code, a variable-length, lossless coding scheme, is applied exclusively to the exponent bits. In this way, data storage savings could be achieved, which can be very significant when the large amount of data has to be stored, such as storing NNs.

The Special Session on Hardware and Software Solutions for Edge AI Applications at the IEEE MIEL 2025 is being organized as part of the EU-funded Horizon Twinning project “Twinning for Excellence in Adaptive Edge AI” (acronym: AIDA4Edge) [1]–[3]. The project is coordinated by the Faculty of Electronic Engineering, University of Niš (FEEUNI), in partnership with the Leibniz Institute for High Performance Microelectronics (IHP), University of Manchester (UoM), and University of Ferrara (UNIFE). AIDA4Edge started on October 1, 2024, and will run for three years. Its main goal is to strengthen scientific, networking and research management capacity of FEEUNI through an intensive collaboration with the advanced partners, enabling FEEUNI to achieve scientific and innovation excellence in the field of Edge AI. Fig. 1 shows the AIDA4Edge logo, and logos of funding institutions.

The application of compression techniques, such as quantization and pruning, to reduce neural network weight size and complexity is gaining momentum due to the significant savings they provide in both hardware and software resources, particularly important for edge devices with limited capabilities. To fully leverage the advantages of these techniques, their design should account for the amplitude dynamics and the probability distribution of the parameters to be compressed. Therefore, it is essential to analyze the statistical characteristics of these parameters prior to compression. Although this type of analysis has been extensively conducted in the context of Artificial Neural Networks (ANNs), it has received limited attention in the case of Spiking Neural Networks (SNNs). Motivated by this gap, this paper examines the statistical properties of the weights of an SNN trained on the DVS128 Gesture dataset. The results of this analysis are valuable not only for enabling a well-founded selection and effective design of appropriate quantization models, but also for supporting the efficient application of pruning techniques, which could benefit from using synaptic weight histograms as valuable guiding information.

The necessity to manage inconsistency in Description Logics Knowledge Bases (KBs) has come to the fore with the increasing importance gained by the Semantic Web, where information comes from different sources that constantly change their content and may contain contradictory descriptions when considered either alone or together. Classical reasoning algorithms do not handle inconsistent KBs, forcing the debugging of the KB in order to remove the inconsistency. In this paper, we exploit an existing probabilistic semantics called DISPONTE to overcome this problem and allow queries also in case of inconsistent KBs. We implemented our approach in the reasoners TRILL and BUNDLE and empirically tested the validity of our proposal. Moreover, we formally compare the presented approach to that of the repair semantics, one of the most established semantics when considering DL reasoning tasks.

Probabilistic Logic Programming combines uncertainty and logic-based languages. Liftable Probabilistic Logic Programs have been recently proposed to perform inference in a lifted way. LIFTCOVER is an algorithm used to perform parameter and structure learning of liftable probabilistic logic programs. In particular, it performs parameter learning via Expectation Maximization and LBFGS. In this paper, we present an updated version of LIFTCOVER, called LIFTCOVER+, in which regularization was added to improve the quality of the solutions and LBFGS was replaced by gradient descent. We tested LIFTCOVER+ on the same 12 datasets on which LIFTCOVER was tested and compared the performances in terms of AUC-ROC, AUC-PR, and execution times. Results show that in most cases Expectation Maximization with regularization improves the quality of the solutions.