Volkan Kursun

Carbon nanotube field effect transistor (CN-MOSFET) is attractive for the realization of future monolithic three-dimensional (M3D) memory circuits with ultra-high integration density, capacity, efficiency, and speed. However, the yield of each vertically-stacked active layer can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) caused by process imperfections. The potential integration density benefits of M3D circuits also may not be fully realized by the large area skews between different layers within standard cells. In this paper, ultra-high density and robust M3D static random-access memory (SRAM) cells are proposed for tolerance to the removal of m-CNs. By minimizing the skew and area of each device layer, the 16Kibit memory arrays with the proposed SRAM cells enhance the integration density by up to 82.92% as compared to the carbon-based traditional 2D and previously published M3D memory arrays. While achieving high functional yield and maintaining robust read/write operations, the proposed SRAM circuits enhance the overall electrical quality by up to 27.41x as compared to the alternative 2D and M3D memory arrays.

A high-yield nine carbon nanotube MOSFET (9-CN-MOSFET) SRAM cell that can tolerate the removal of metallic carbon nanotubes (m-CNs) is proposed in this paper. A functional yield model of carbon nanotube transistors and memory circuits is developed considering the spatial correlations of CNs in the channel arrays. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by 21309x as compared to the previously published memory circuit that does not consider process imperfections. The read delay and worst-case write delay of the proposed 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit in a 16nm CN-MOSFET technology.

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new FinFET memory circuits with asymmetrically gate underlap engineered transistors are proposed in this paper for achieving stronger read data stability and lower leakage power consumption. With the proposed asymmetrical six-transistor SRAM cells, read data stability is enhanced by up to 72.2% while maintaining similar write voltage margin and layout area as compared to the conventional symmetrical six-transistor SRAM cells in a 15nm FinFET technology. Furthermore, leakage power consumption is reduced by up to 37.4% with the proposed asymmetrical FinFET SRAM cells as compared to the conventional six-FinFET SRAM cells with symmetrical transistors.

A new variable strength keeper technique is presented in this paper for achieving higher-speed and lower-leakage currents in wide fan-in dynamic logic gates with carbon nanotube transistors. The strength of the keeper is dynamically adjusted depending on the logical state of the dynamic node during evaluation phase in a domino logic circuit. While providing similar noise immunity, the evaluation delay and power-delay product of the proposed domino logic circuits are reduced by up to 13.33% and 13.84%, respectively, as compared to the standard domino logic circuits in a 16nm carbon nanotube transistor technology. Furthermore, the proposed technique provides up to 77.98% savings in average leakage power consumption as compared to the standard domino logic circuits in idle mode.

Leakage power that is consumed by gigascale clock distribution networks is an important challenge in modern synchronous integrated circuits with billions of deeply-scaled transistors. A novel dual-threshold-voltage repeater circuit with split inputs and outputs is employed for achieving enhanced power efficiency in clock distribution networks in this paper. With the new repeaters, the mean of the statistical leakage power consumption distribution is reduced by up to 39.6% without increasing the layout area, active power consumption, clock skew, and clock period as compared to a conventional clock distribution network with standard static CMOS inverter based repeaters in a TSMC 65nm CMOS technology.

A new single-ended read asymmetrical SRAM cell with underlap engineered symmetrical FinFETs is proposed in this paper for achieving stronger data stability, enhanced write ability, and suppressed leakage power consumption as compared to previously published six-FinFET memory circuits. With the new SRAM cell, the read data stability, read speed, write voltage margin, and write speed are enhanced by up to 2.7×, 57.6%, 25.5%, and 20.1% while the leakage power consumption is reduced by up to 69.8% without degrading the memory integration density as compared to the previously published six-FinFET SRAM cells in a 15nm FinFET technology.