Liansheng Huang

This paper proposes a novel dual-loop voltage-current control scheme for a three-phase three-level converter system. In the voltage-loop, a variable-exponential-gain mechanism is introduced, enabling the proposed controller to combine the benefits of proportional-integral (PI) control and super-twisting algorithm (STA). Moreover, time-varying control gains are coupled with the variable-exponential-gain to match the controller characteristics across operating conditions. A Lipschitz-continuous function is further introduced to mitigate chattering. The voltage-loop performance under steady-state and dynamic constraints is validated via Monte Carlo sensitivity analysis. For the current-loop, a feedback-parallel optimization finite-control-set model predictive control strategy is proposed. By partitioning the space into small triangular sectors and applying boundary mapping, the number of candidate voltage vectors is reduced. A vector selection mechanism is then formulated to minimize the tracking errors along the $\alpha$ and $\beta$ axes in parallel. In addition, the previously selected optimal voltage vector enforces level matching between the $\alpha$/$\beta$ components, which identifies the axis to prioritize for post-minimization fine-tuning. The weighting coefficient is eliminated using the sign-matching principle, thereby reducing computational complexity. For the voltage-loop, uniform ultimate boundedness and robustness bound analysis are provided. For the current-loop, the neutral-point potential suppression mechanism without a weighting coefficient is analyzed, and a single-step error boundedness proof is established. Simulation and experimental results validate the superiority of the proposed dual-loop control scheme.

The three-phase grid-tied PWM converter in the DC bus system is utilized to achieve energy conversion. Due to the influence of factors such as time and temperature on sensors or conditioning circuits, the measured AC current values may have scaling and DC offset errors, leading to the imbalance and DC biases in the three-phase currents. It will affect the quality of electrical energy on the AC side, which is detrimental to the long-term stable operation of the system. Given that the voltage fluctuations of DC buses are influenced by various loads, traditional compensation strategies for current measurement errors cannot be directly applied. Therefore, this paper proposes an AC current measurement error compensation strategy for the three-phase PWM converter in the DC bus system. The scaling error compensation coefficient is obtained by sequentially superimposing a DC value on the three-phase measured currents, and the DC offset error is obtained by sequentially blocking and clamping the three-phase bridge arms. The proposed strategy compensates for AC current measurement error without using DC voltage and current information, making it more suitable for the three-phase PWM converter in the DC bus system. Simulation and experimental results validate the effectiveness of the proposed compensation strategy.

In the Experimental Advanced Superconducting Tokamak (EAST) poloidal-field power supply (PFPS), the necessity of paralleling high-power IGBT modules within each IGBT bridge arm unit is underscored by substantial power requirements. This study aims to enhance current sharing among these modules, focusing on module layout and copper bar structure optimization. Utilizing the partial element equivalent circuit (PEEC) method, we model the stray inductance in the commutation circuit, considering the skin and proximity effects in laminated busbars. A novel input structure is proposed to improve the current sharing without affecting the unit’s overall inductance, incorporating heat dissipation and dc-link capacitor layout into the bridge arm unit’s design. This article’s main contributions include detailed PEEC-based electromagnetic modeling and a new design enhancing current sharing in 3IGBT parallel modules, validated by multiphysics co-simulation. These simulations confirm our approach meets the system’s compatibility, stress, current sharing, and temperature criteria, marking significant progress in high-power IGBT module application in fusion power systems. This article not only presents a practical solution to current-sharing challenges but also sets the groundwork for future advancements in power electronics design.

PWM output delay caused by calculation is widely presented in permanent magnet synchronous motor drive systems, which reduces control performance, accuracy, and stability. This article proposes a novel enhanced SVPWM update strategy, which is easy to implement and achieves completely delay-free output. Compared to traditional methods, this approach is simpler to compute, does not rely on motor parameters, and does not require an increase in sampling frequency. The effectiveness and superiority of the proposed algorithm are verified through comparative experiments.

For high-power paralleled three-phase three-level inverters with low switching frequency requirements, a novel cell-by-cell-based (CBCB) finite control set model predictive control algorithm is proposed in this article. First, the CBCB framework involves two individual inverters with staggered control timings, differing by half a period. Second, within the CBCB framework, a delay compensation solution with smaller estimation errors is expounded. Furthermore, a novel cost function for each individual inverter is designed, resulting in a doubling of the equivalent control frequency. Third, to improve the computational efficiency, candidate voltage vectors are preselected under the constraint of phase voltage jump and the requirement for low phase circulating current (PCC). Compared to the conventional decentralized FCS-MPC algorithm and the existing optimization algorithms, the proposed algorithm significantly reduces current harmonics and has a faster dynamic response rate at low average switching frequencies. Meanwhile, PCC is well suppressed. Besides, the above advantages are robust when the electric-circuit parameters are mismatched in the control system. Experimental results are provided to validate the advantages of the proposed algorithm.

The computational complexity of the three-level space vector pulse width modulation (SVPWM) limits its application in high-switching-frequency converters. To address this issue, this paper proposes a simplified SVPWM algorithm based on virtual chopping. Firstly, the reference voltage vector (VV) is adjusted to avoid excessive line-to-line voltage jumps. Secondly, boundary VVs in the space vector diagram, with simple switching sequences, are chosen as standards. Thirdly, the switching sequence of the reference VV is determined by virtual chopping the corresponding standard VV’s. Furthermore, to generate it in the microcontroller, the corresponding modulation waves are obtained. Finally, a method to balance DC side capacitor voltages is proposed. Consequently, the proposed algorithm simplifies the process, requiring only four equations. The sector determination, dwell time calculation and allocation are bypassed. Compared with the existing algorithms, the execution time and design complexity of the proposed algorithm in the microcontroller is reduced. Experimental results are presented to verify its effectiveness.

This article used co-simulation with ANASYS, Simplorer, and MATLAB/Simulink to design a phase output bar (POB) for achieving equal static and dynamic current sharing among three parallel insulated-gate bipolar transistors (IGBTs) in a bridge arm of Super-conducting Tokamak (EAST) poloidal field power supply (PFPS). A separated output bar structure is proposed, and the bus structure is modeled parametrically. Q3D was used to extract the POB’s stray inductance to compare and evaluate. The influence on stray inductance and steady-state current distribution of various degrees of separation structures is evaluated and compared. The structure design was optimized to obtain a more uniform stray parameter distribution. Asynchronous Gate Signal Driving Method is introduced to improve dynamic current sharing. Through multi-physical field and circuit co-simulation, the whole module is verified by system-level simulation. The maximum ratio of the three IGBT modules’ imbalanced current (MRIC) is within 5%. The current sharing performance with the designed POB was verified. Finally, a power stack with a dc-link voltage of 1700 V based on three parallel IGBTs was constructed. The co-simulation results indicated the effectiveness of the proposed design for the POB. The bridge arm module has been applied in the EAST polar field power supply PS11 and PS12.

The severe voltage oscillation of SiC MOSFET in switching transient affects the safety of devices and EMI. In this article, a series capacitance gate driver (SCGD) is proposed to solve this problem. The series capacitance is charged or discharged in switching transient so that the equivalent driving resistance is gradually increased compared with that of conventional gate driver (CGD), and the voltage oscillation is suppressed. Under the same voltage oscillation level, the average equivalent driving resistance of SCGD is smaller than that of CGD through reasonable parameters design. This means that the optimization of both voltage oscillation and switching loss is realized. Although active gate driver (AGD) has good performance in this respect, the effect may be affected by the delay and control accuracy due to very short switching transient time of SiC MOSFET. Compared with AGD, the proposed SCGD only adds passive components without any control and has a simple structure. The experimental results verify the effectiveness of SCGD.