Jose Rodrigo Azambuja

Convolutional Neural Networks (CNNs) are increasingly used for on-board image classification in satellites and aerial vehicles, but their deployment on SRAM-based FPGAs and All-Programmable System-on-Chip (APSoC) is limited by radiation-induced faults. This work introduces URSA, a reconfigurable Systolic Array (SA) accelerator for CNN inference implemented on AMD Xilinx Zynq-7000 devices. URSA allows design-time configurability of array geometry and memory organization, enabling the systematic experimental evaluation of how these architectural choices interact with fault-tolerance techniques to determine system-level reliability. A heavy-ion irradiation campaign at the SAFIIRA facility evaluated multiple URSA variants against naive and Arm-based baselines, considering Triple Modular Redundancy (TMR), configuration scrubbing, and Error Detection and Correction (EDAC). Results show that URSA consistently outperforms baselines, that combining TMR and scrubbing provides the most effective resilience improvements, and that OCM-based configurations outperform BRAM-based ones due to reduced programmable logic exposure. From these results, four architectural design guidelines are derived, providing quantified, experimentally validated recommendations for systolic-array CNN accelerators in radiation-prone environments.

Motivated by the increasing adoption of COTS microcontrollers in New Space missions, this work investigates the behavior of Arm Cortex-M Systems-on-Chip running computational workloads under FreeRTOS with the Core Flight System (cFS) middleware. The research focuses on how cFS interactions and cache configurations influence fault behavior under neutron irradiation. The experiments reveal that incorporating a cache significantly increases all software failure rates, and that adding cFS leads to a higher incidence of I/O-related timeouts. Postmortem analysis of processor states indicated that many timeout events were not indicative of actual operational errors but rather triggers of hardware and software exceptions. Detailed execution tracing revealed that these timeouts were exceptions, and enabling the CPU cache fundamentally altered the fault profile. This finding underscores the importance of understanding how OS-level fault detection and recovery contribute to system reliability under radiation-induced stress.

This study examines the performance of two Convolutional Neural Networks (CNNs) designed for aerial image classification in the presence of radiation-induced bit-flips. We modify these CNNs by adjusting parameters such as quantization and parallelism to facilitate their implementation using the FINN inference engine, which is optimized for the AMD/Xilinx FPGAs. The aim is to evaluate the impact of different quantization levels, network topologies, and architectural parallelism on area, computational performance, and reliability in the presence of soft-errors. Emulated fault injection and heavy ion irradiation were performed. The results indicate that the same CNN topology can exhibit up to a 2.7× difference in Mean Fluence to Failure (MΦTF) by altering quantization and architectural parallelism. The findings demonstrate that higher dependability can be obtained by carefully combining a suitable CNN topology with optimized quantization and architectural parallelism.

A Virtualização de Funções de Rede (NFV) tornou-se fundamental para o provisionamento escalável de serviços de redes, e o posicionamento e encadeamento de funções de rede (VNFPC) assume um papel crítico nesse contexto. Apesar da intensa atividade de pesquisa em VNFPC, as soluções existentes não consideram que o plano de dados pode ser programável e multi-tenant. Por um lado, algumas funções de rede customizadas podem necessitar de mecanismos como in-band telemetry ou de protocolos também customizados implementados em switches programáveis ao longo do caminho na rede. Por outro lado, a implantação de switches para atender às necessidades de funções de rede específicas pode afetar também os demais fluxos na rede. Neste artigo, discutimos a nova camada de complexidade que a programabilidade do plano de dados adiciona ao VNFPC, e propomos uma primeira solução a esse problema, a qual explora multi-tenancy em switches programáveis para escalonar switches virtuais que processam os fluxos de funções de rede.

This work investigates the impact of neutron and heavy ion radiation-induced soft errors on Arm Cortex-M Systems-on-Chip and proposes a fault injection methodology designed for the early assessment of these effects on the embedded processors. Our methodology is then employed to assess the effectiveness of software design exploration and implementing fault tolerance techniques. We connect heavy ion and neutron radiation experiments and emulate fault injections for applications running on these resource-constrained low-cost processors. Our case studies include benchmark scenarios with bare-metal applications and the FreeRTOS operating system, tailored for deployment in small satellite missions. Results show that our proposed methodology presents reliability curves that align with those obtained from the radiation experiments.

This study investigates the impacts of radiation-induced soft errors on system-on-chips with Arm Cortex-M microprocessors. We evaluate two Cortex-M microprocessors running two applications. Regarding their use in mission-critical and safety-critical applications, we explore multiple scenarios, considering single, parallel, and periodic tasks, bare-metal and light operating system execution, and caches enabled and disabled. We tested two microprocessor devices under 14 MeV neutrons to draw a preliminary reliability analysis, measuring performance and reliability metrics under radiation-induced soft errors. Finally, we discuss trade-offs between performance and reliability, providing insights into how the Arm Cortex-M microprocessor series performs in harsh environments. Results can aid designers in developing more efficient and reliable fault tolerance techniques to enable such microprocessors to operate in aerospace applications.

Modern Systems on Chip (SoC), almost as a rule, require accelerators for achieving energy efficiency and high performance for specific tasks that are not necessarily well suited for execution in standard processing units. Considering the broad range of applications and necessity for specialization, the design of SoCs has thus become expressively more challenging. In this paper, we put forward the concept of G-GPU, a general-purpose GPU-like accelerator that is not application-specific but still gives benefits in energy efficiency and throughput. Furthermore, we have identified an existing gap for these accelerators in ASIC, for which no known automated generation platform/tool exists. Our solution, called GPUPlanner, is an open-source generator of accelerators, from RTL to GDSII, that addresses this gap. Our analysis results show that our automatically generated G-GPU designs are remarkably efficient when compared against the popular CPU architecture RISC- V, presenting speed-ups of up to 223 times in raw performance and up to 11 times when the metric is performance derated by area. These results are achieved by executing a design space exploration of the GPU-like accelerators, where the memory hierarchy is broken in a smart fashion and the logic is pipelined on demand. Finally, tapeout-ready layouts of the G-GPU in 65nm CMOS are presented.