Xufeng Kou
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Xufeng Kou has a total of 511 co-authors. Here are the top co-authors by number of shared publications:
- Kang. L. Wang
Department of Electrical and Computer Engineering University of California Los Angeles California USA
24 shared publications Kang L. Wang
Department of Electrical and Computer Engineering, University of California 2 , Los Angeles, California 90095
23 shared publicationsYabin Fan
Department of Electrical and Computer Engineering, Department of Physics, and Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095, USA
20 shared publications- Yong Wang
Zhejiang University
19 shared publications - Jin Zou
School of Mechanical and Mining Engineering, and Centre for Microscopy and Microanalysis, The University of Queensland, Brisbane, Australia
17 shared publications Liang He
Department of Electrical Engineering, University of California, Los Angeles, CA 90095
17 shared publications
Latest Publications
- 1 December 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41 (12) , 21347-21357
A Hybrid Switched-Capacitor CDR 48 V/1 V Voltage Regulator
- 1 December 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41 (12) , 21347-21357
A Hybrid Switched-Capacitor CDR 48 V/1 V Voltage Regulator
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6284-6299
A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6284-6299
A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6547-6560
CTH-CAM: A Cryogenic eDRAM-Based CAM With 1--26 Tunable Hamming Distance
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6547-6560
CTH-CAM: A Cryogenic eDRAM-Based CAM With 1--26 Tunable Hamming Distance
- Open Access
- 30 October 2026
- Published by Springer Nature in Nature Communications
Observation of quantized charge accumulation in a quantum anomalous Hall system
- 30 October 2026
- Published by Springer Nature in Nature Communications
Open AccessObservation of quantized charge accumulation in a quantum anomalous Hall system
- 8 October 2026
- Published by American Association for the Advancement of Science (AAAS) in Science
- Vol. 394 (6820) , 222-227
Wafer-scale low-symmetry graphene moiré superlattice for integrated quantum rectifiers
Low-symmetry materials unlock rich Berry curvature physics and anomalous transport phenomena that are forbidden in high-symmetry quantum systems through rigorous crystalline symmetry constraints. Current approaches rely on external fields or complex heterogeneous stacking to break crystalline symmetries, which hinders scalable device integration. In this work, we demonstrate surface premelting engineering to create wafer-scale low-symmetry graphene on germanium-110 [Ge(110)]. Controlled premelting forms striped germanium surface patterns that reduce graphene symmetry from D 6h to C 1v , producing a room-temperature nonlinear Hall conductivity of ~11 micrometers per volt per ohm. First-principles calculations attribute this to originating from overtilted massive Dirac cones of hybridized germanium bands and the graphene Dirac cone. Integrated nonlinear Hall rectifiers generate >20 millivolts of output from radio frequency input and drive commercial voltage boosters and light-emitting diodes, establishing a complementary metal-oxide semiconductor–compatible route toward wafer-scale nonlinear quantum devices.
- 8 October 2026
- Published by American Association for the Advancement of Science (AAAS) in Science
- Vol. 394 (6820) , 222-227
Wafer-scale low-symmetry graphene moiré superlattice for integrated quantum rectifiers
Low-symmetry materials unlock rich Berry curvature physics and anomalous transport phenomena that are forbidden in high-symmetry quantum systems through rigorous crystalline symmetry constraints. Current approaches rely on external fields or complex heterogeneous stacking to break crystalline symmetries, which hinders scalable device integration. In this work, we demonstrate surface premelting engineering to create wafer-scale low-symmetry graphene on germanium-110 [Ge(110)]. Controlled premelting forms striped germanium surface patterns that reduce graphene symmetry from D 6h to C 1v , producing a room-temperature nonlinear Hall conductivity of ~11 micrometers per volt per ohm. First-principles calculations attribute this to originating from overtilted massive Dirac cones of hybridized germanium bands and the graphene Dirac cone. Integrated nonlinear Hall rectifiers generate >20 millivolts of output from radio frequency input and drive commercial voltage boosters and light-emitting diodes, establishing a complementary metal-oxide semiconductor–compatible route toward wafer-scale nonlinear quantum devices.
- 1 September 2026
- Published by AIP Publishing in Applied Physics Reviews
- Vol. 13 (3)
Spin orbit torque magnetic tunneling junction for noise-tolerant and resource-saving probabilistic binary neural network
The deployment of large-scale 32-bit neural networks is hindered by the escalating parameter sizes and inherent susceptibility to noise. Here, we present a nonvolatile memory (NVM)-based probabilistic computing architecture, which harnesses both the stochastic nature and in-memory computing capabilities of NVM to enhance computation efficiency and robustness. Utilizing in-plane magnetized spin–orbit torque magneto-resistive random-access memory (i-SOT) cells, we demonstrate ultra-fast (400 ps) all-electrical switching, 1011 data endurance, and voltage-controllable probabilistic states with a low variation of 3.8%. These features enable the implementation of an on-chip SOT probabilistic binary neural network (SOT-PBNN) hardware, achieving near-baseline accuracy (88.2%) on CIFAR-10 classification tasks. Moreover, the stochastic training process endows the SOT-PBNN to attain a sevenfold improvement in classification accuracy over its 32-bit convolutional neural network counterpart under 25% write/read noise, while reducing the parameter size and inference energy by 1–2 orders. Our work establishes a lightweight framework suitable for realizing artificial intelligence platforms on resource-constrained edge devices.
- 1 September 2026
- Published by AIP Publishing in Applied Physics Reviews
- Vol. 13 (3)
Spin orbit torque magnetic tunneling junction for noise-tolerant and resource-saving probabilistic binary neural network
The deployment of large-scale 32-bit neural networks is hindered by the escalating parameter sizes and inherent susceptibility to noise. Here, we present a nonvolatile memory (NVM)-based probabilistic computing architecture, which harnesses both the stochastic nature and in-memory computing capabilities of NVM to enhance computation efficiency and robustness. Utilizing in-plane magnetized spin–orbit torque magneto-resistive random-access memory (i-SOT) cells, we demonstrate ultra-fast (400 ps) all-electrical switching, 1011 data endurance, and voltage-controllable probabilistic states with a low variation of 3.8%. These features enable the implementation of an on-chip SOT probabilistic binary neural network (SOT-PBNN) hardware, achieving near-baseline accuracy (88.2%) on CIFAR-10 classification tasks. Moreover, the stochastic training process endows the SOT-PBNN to attain a sevenfold improvement in classification accuracy over its 32-bit convolutional neural network counterpart under 25% write/read noise, while reducing the parameter size and inference energy by 1–2 orders. Our work establishes a lightweight framework suitable for realizing artificial intelligence platforms on resource-constrained edge devices.
- 1 June 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (6) , 1125-1128
12-in Bottom-Pinned VCMA-MRAM Devices With 0.6 ns Switching Speed, 30 fJ/bit Write Energy, and 10 14 Endurance
This letter reports high-performance VCMA-MRAM devices fabricated on 12-inch wafer. By leveraging a bottom-pinned MTJ stack and synthetic antiferromagnet engineering, the optimized structure reduces stray field to 1.5 mT, enabling highly symmetric switching with a VCMA coefficient of 71.2 fJ/V$\cdot $ m. Meanwhile, a thicker MgO barrier enhances device robustness and endurance exceeding$\mathbf {{10}}^{\mathbf {{14}}}$ cycles. Moreover, the devices sustain fast voltage-driven switching down to 0.6 ns while maintaining a low write energy of 30 fJ/bit, surpassing prior state-of-the-art MRAM counterparts. Our results establish bottom-pinned VCMA-MRAM as a promising candidate for ultra-fast, energy-efficient, and high-endurance embedded nonvolatile memory.- 1 June 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (6) , 1125-1128
12-in Bottom-Pinned VCMA-MRAM Devices With 0.6 ns Switching Speed, 30 fJ/bit Write Energy, and 10 14 Endurance
This letter reports high-performance VCMA-MRAM devices fabricated on 12-inch wafer. By leveraging a bottom-pinned MTJ stack and synthetic antiferromagnet engineering, the optimized structure reduces stray field to 1.5 mT, enabling highly symmetric switching with a VCMA coefficient of 71.2 fJ/V$\cdot $ m. Meanwhile, a thicker MgO barrier enhances device robustness and endurance exceeding$\mathbf {{10}}^{\mathbf {{14}}}$ cycles. Moreover, the devices sustain fast voltage-driven switching down to 0.6 ns while maintaining a low write energy of 30 fJ/bit, surpassing prior state-of-the-art MRAM counterparts. Our results establish bottom-pinned VCMA-MRAM as a promising candidate for ultra-fast, energy-efficient, and high-endurance embedded nonvolatile memory.- 20 April 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (6) , 1225-1228
Sub-0.2 V- V TH Cryo-CMOS Technology via Halo Implantation and Metal-Gate Engineering
We report a 28-nm low-power cryogenic CMOS (Cryo-CMOS) technology for energy-efficient computing. The precise adjustments of metal-gate thickness and halo implants manage to compensate the threshold voltage (${V}_{\text {TH}}\text {)}$ shift at low temperatures. The optimized cryogenic transistors are featured by${V}_{\text {TH}} \lt 0.2$ V, sub-threshold swing < 33mV/dec, and elevate the saturation current level (${I}_{\text {DSAT}}\gt 1.3$ mA/$\mu $ m) by$1.74\times \sim 3.71\times $ compared to uLVT/RVT counterparts at 77 K. Combined with a reduced global device variability, the low-${V}_{\text {TH}}$ devices warrant a reliable sub-0.6V operation with an on/off ratio$\gt 10^{{7}}$ , reducing the total power consumption of the ring oscillator by 37% at 77 K.- 20 April 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (6) , 1225-1228
Sub-0.2 V- V TH Cryo-CMOS Technology via Halo Implantation and Metal-Gate Engineering
We report a 28-nm low-power cryogenic CMOS (Cryo-CMOS) technology for energy-efficient computing. The precise adjustments of metal-gate thickness and halo implants manage to compensate the threshold voltage (${V}_{\text {TH}}\text {)}$ shift at low temperatures. The optimized cryogenic transistors are featured by${V}_{\text {TH}} \lt 0.2$ V, sub-threshold swing < 33mV/dec, and elevate the saturation current level (${I}_{\text {DSAT}}\gt 1.3$ mA/$\mu $ m) by$1.74\times \sim 3.71\times $ compared to uLVT/RVT counterparts at 77 K. Combined with a reduced global device variability, the low-${V}_{\text {TH}}$ devices warrant a reliable sub-0.6V operation with an on/off ratio$\gt 10^{{7}}$ , reducing the total power consumption of the ring oscillator by 37% at 77 K.- 7 April 2026
- Published by AIP Publishing in Applied Physics Reviews
- Vol. 13 (2)
Deterministic polarity control of self-generated spin–orbit torque via inversion symmetry engineering
Self-generated spin–orbit torque (SOT) in magnetic materials has emerged as a promising pathway for efficient magnetization control without external spin current sources. Here, we unveil an alternative mechanism for deterministic SOT polarity control based on inversion symmetry engineering via ferromagnet (Co) thickness gradients in [Co/Pt]p multilayers with the repeating periods p. Unlike conventional approaches relying on spin Hall effect asymmetry in heavy metals, we modulate the spatial profile of spin current absorption and reflection across the stack, creating a net damping-like SOT driven by gradient-induced imbalanced spin accumulation. By inverting the Co gradient, we achieved polarity-reversed perpendicular magnetization switching, demonstrating that the SOT originates from structural symmetry breaking within the ferromagnetic layers. Second harmonic measurements confirm robust SOT switching efficiencies up to 294 Oe cm2 MA−1, along with enhanced thermal stability and scalability beyond bilayer systems. Our findings establish the symmetry-governed design principle for spin transport, enabling tunable and thickness-robust spintronic devices.
- 7 April 2026
- Published by AIP Publishing in Applied Physics Reviews
- Vol. 13 (2)
Deterministic polarity control of self-generated spin–orbit torque via inversion symmetry engineering
Self-generated spin–orbit torque (SOT) in magnetic materials has emerged as a promising pathway for efficient magnetization control without external spin current sources. Here, we unveil an alternative mechanism for deterministic SOT polarity control based on inversion symmetry engineering via ferromagnet (Co) thickness gradients in [Co/Pt]p multilayers with the repeating periods p. Unlike conventional approaches relying on spin Hall effect asymmetry in heavy metals, we modulate the spatial profile of spin current absorption and reflection across the stack, creating a net damping-like SOT driven by gradient-induced imbalanced spin accumulation. By inverting the Co gradient, we achieved polarity-reversed perpendicular magnetization switching, demonstrating that the SOT originates from structural symmetry breaking within the ferromagnetic layers. Second harmonic measurements confirm robust SOT switching efficiencies up to 294 Oe cm2 MA−1, along with enhanced thermal stability and scalability beyond bilayer systems. Our findings establish the symmetry-governed design principle for spin transport, enabling tunable and thickness-robust spintronic devices.