Vadim Issakov

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In this paper we present a 140 GHz transceiver front-end in 45 nm SOI CMOS. The transmitter achieves a measured an EIRP of 15 dBm using on-antenna and in-air power combining techniques in a multi-port slot-dipole-array without additional fabrication techniques like backside etching or dielectric lenses. On the receiver side, a passive leakage cancellation circuit between two on-chip slot-dipoles protects the LNA from blocking due to TX / RX-leakage. The measured EINF (Equivalent Isotropic Noise Figure) and receiver gain are 6.2 dB and 12.5 dB, respectively. The complete transceiver consumes 452mA from a 1.8V supply and measures 2.5mm × 2 mm. To the best of the authors’ knowledge, the presented work is the first transceiver frontend, which employs both on-antenna- and in-air combining, as well as antenna-based leakage cancellation techniques applied at D-band frequencies.

This letter presents a fractional-N charge-pump phase-locked loop (CP-PLL) operating at cryogenic temperatures (CT) down to 6 K. The phase-locked loop (PLL), generating signals in the frequency range around 2.28–2.68 GHz, is intended as a reference source in a microwave signal generator for a trapped-ion quantum computer operating with ${}^{{9}}\text {Be}^{\text {+}}$ ions. Using a third-order MASH DSmodulator (DSM), the PLL achieves a highly competitive FoM of −245 dB. The circuit exhibits the highest fractional spur suppression among the recently reported cryogenic PLLs, as well as the lowest chip area.

This work presents a cross-voltage domain instrumentation amplifier (INA) based electrode signal processing (ESP) unit for providing full-scale (FS) voltage ranges in excess of 10V at the electrodes of a trapped-ion quantum computer (TIQC) at cryogenic temperatures (CT). It carries out a systematic comparison between a reference design and the proposed INA approach. While both designs achieve their targeted specifications at room temperature (RT), the reference ESP unit’s linearity and noise performance deteriorates at CT. In contrast, the proposed INA-based ESP unit maintains its linearity and noise performance down to 5 K. Both designs are fabricated in a 130nm BCD technology and are evaluated under identical measurement conditions. Measurement results demonstrate that the proposed INA-based ESP unit greatly improves upon the reference design. At 5K its integrated RMS noise improves from 10.2 mVrms to 0.9 mVrms, while its SFDR improves by 25 dB to 49.9 dB and its power is reduced by about 11mW down to 19.5mW.

In this paper, we introduce a novel low-power radar-based gesture sensing system specifically designed for portable devices with stringent energy efficiency requirements. Traditional approaches often rely on range-Doppler images and deep learning models, which can be computationally intensive and power-hungry. Our system directly processes raw ADC data from radar signals, employing independent component analysis (ICA) to extract essential features for gesture recognition. These features are utilized by a novel spiking neural network (SNN), which is inherently energy-efficient due to its sparse time encoding and event-driven operation. Experimental results demonstrate that our system achieves a remarkable accuracy of 99.98% while maintaining a compact model size, making it highly suitable for deployment in portable devices.

In this brief, we present design considerations on achieving highest figure of merit (FoM) for a class-B LC VCO in CMOS. Following aspects are addressed: a) systematic analysis of choosing the optimal fundamental oscillation frequency $f_{\text {O}}$ for achieving simultaneously low phase noise (PN) and high power efficiency, i.e., highest FoM. We show that the optimal $f_{\text {O}}$ is directly related to the frequency tuning range (FTR). E.g., in the given technology, an FTR of 3% results in an optimal operating range of 10 GHz to 20 GHz. A wider FTR narrows down the operation range for optimal PN and FOM; and b) we present an LC-tank step-by-step dimensioning procedure. The proposed approach is based on iterative electromagnetic (EM)-simulations of the resonant circuit components and optimization with respect to technology-independent design degrees of freedom. The terms $\mathbf {10{\,}\mathrm {\mathbf {log_{10}}}(L/(CR_{\mathrm {T}}))}$ and $\mathbf {20{\,}\mathrm {\mathbf {log_{10}}}(R_{\mathrm {T}}\sqrt {C/L})}$ derived from analytical expressions for PN and FoM are optimized over frequency for various $\mathbf {{C_{\max }}/{C_{\min }}}$ ratios. We use these considerations to design a multi-harmonic class-B LC-VCO in 22 nm FDSOI CMOS, which offers two outputs - one at the fundamental (H1) and another at the fourth harmonic (H4), extracted directly from the core. The VCO achieves a highly competitive FoM at 1 MHz offset with 0.4 V supply of 193.8 dBc/Hz and 188.2 dBc/Hz at 20 GHz and 80 GHz, respectively. We demonstrate that class-B VCO can achieve PN and FoM outperforming class-C or class-F. It is achieved only by means of the proposed systematic LC-tank design, without any additional circuitry, such as waveform shaping, core coupling etc. Thus, core area is only $\mathbf {0.05{\,}\mathrm {\mathbf {mm^{2}}}}$ .

There are multiple microwave breast imaging (MBI) systems that are already conducting clinical trials. One common feature of these systems is the use of expensive radio-frequency (RF) laboratory equipment, such as vector network analyzers (VNA). To replace the VNA in an MBI setup with a significantly more cost-effective radar system, it is necessary to derive suitable hardware specifications. A fundamental parameter is the dynamic range, defined as the ratio of the maximum to the minimum usable signal power. A modern VNA can support a dynamic range of more than 120 dB. However, it might not be necessary for the radar system to match the VNA's dynamic range specifications. This is because the MBI setup itself affects the usable dynamic range. In this work, we investigate how much the usable dynamic range of an MBI setup is limited by clutter and noise. For this purpose, we utilize a frequency-modulated continuous-wave (FMCW) radar system operating from 6–14 GHz. Our results demonstrate the need to analyze the entire imaging setup rather than a single component to define the appropriate hardware parameters.

We combine a cryogenic BiCMOS integrated circuit, which generates high-speed return-to-zero (RTZ) pulses, with a superconducting Josephson junction array. The BiCMOS circuit acts as a cryogenic pulse pattern generator, delivering data rates of 30 Gb/s, while consuming 302 mW at 4 K. Each electrical pulse of the serializer effectively transfers one magnetic flux quantum through every Josephson junction, so that the average output voltage of the array produces well-defined plateaus (Shapiro steps) in its current-to-voltage characteristic. To the best of our knowledge, this is the first integration of a Josephson junction array with a cryogenic BiCMOS chip. The presented results pave the way toward a hybrid and fully integrated Josephson arbitrary waveform synthesizer (JAWS) that can generate ultra-low-noise signals for quantum voltage metrology and quantum information systems.

This article presents a source-follower (SF) and charge-pump (CP)-based amplification that is linear and bias-calibration-free across a wide temperature range from 4.2 to 373 K, targeting pipelined analog-to-digital converters (ADCs). While prior SF and CP-based amplifiers suffer from poor linearity because the SF must drive large amplified signals, we propose a buffer-then-amplify (BTA) CP architecture that relocates the CP to the SF output. As a result, the SF only buffers unamplified small-swing residues, fully exploiting its intrinsic linearity and eliminating the need for high-order gain calibrations even in advanced process nodes. To further enhance robustness and efficiency, we introduce an adaptively biased class-AB SF. An integrated active-hold technique is also proposed to eliminate the timing and bandwidth mismatch between the first-pipeline-stage sampling capacitor and the sub-ADC by repurposing the SF as a hold buffer for the sub-ADC. The prototype 12-bit 800-MS/s pipelined time-interleaved successive approximation register (TI-SAR) ADC is fabricated in 12-nm FinFET technology. It achieves SNDR higher than 55.0 dB across the 4.2–373 K temperature range with 40-MHz input, and peak Walden figure-of-merit (FoM_W) of 9.2 fJ/c.-step at 4.2 K. To the best of the authors’ knowledge, the achieved functional temperature range is the widest among >10-bit >300-MS/s ADCs.

This article presents a cryo-BiCMOS system on chip (SoC) designed for single and two-qubit gate operations for quantum computers (QCs) based on beryllium trapped-ions (TIs). Signal generation from 0.7 to 1.6 GHz is supported, covering all microwave transitions in a ${}^{9}\text {Be}^{+}$ QC realization. An integrated 48-kbit waveform memory is implemented for improved two-qubit gate fidelity. The fabricated IC is verified in a 4 K environment with up to 4 qubits, thus enabling quantum processor unit (QPU) cointegration. IC operation up to RT ensures compatibility with future system realizations. Measurements demonstrate qubit state control with an oscillation amplitude of 94% before SPAM correction and Rabi oscillation rate of 172 kHz. Evaluations of long sequences of $\sigma _{x}$ gates indicate control of the quantum state with high quality. Interaction with one computational zone is possible at a total power consumption of 86 mW translating to 21.5 mW/qubit in the presented measurements. Comparison with the state-of-the-art controller reveals drastic power and form-factor reduction at comparable performance, thus paving the way for a scalable TI platform. The chip is fabricated in a 0.13- $\mathrm {\mu }\mathrm {m}$ SiGe BiCMOS technology. To the best of our knowledge, this is the first reported from-scratch system design for TI-based QC concluding with a qubit state manipulation demonstration.