Wen Hsin Chang

Indium-based (In-based) oxide semiconductor channels fabricated by atomic layer deposition (ALD) become a promising candidate for back-end of line (BEOL) transistors and memory devices integrated with advanced CMOS technology. Although high reactivity plasma-enhanced ALD (PEALD) effectively removed the impurity ligands, the incorporation of excess oxygen into oxide semiconductor channels introduces the acceptor-like traps, which degrade device performance and bias stability. In this work, we characterize PEALD AlOx-passivated InOx FETs with channel thickness ranging from 1.8 to 2.6-nm, under different annealing ambient and temperatures. The 1.8-nm InOx FET subjected to oxidizing annealing shows current degradation, voltage hysteresis, and bias instability due to subgap trap formation caused by excess oxygen incorporation. Increasing the channel thickness to 2.6-nm mitigates these issues by reducing the interfacial effect from accumulated oxygen. This study provides design guidelines for BEOL-compatible oxide semiconductor FET fabricated by PEALD, enabling monolithic 3-dimensional integration.

The online version contains supplementary material available at 10.1038/s41598-026-41610-3.

For the first time, highly integrated IGZO transistors suitable for back-end-of-line (BEOL) integration are demonstrated, leveraging an in-situ ozone interfacial layer (IL) treatment before HfO deposition. The ozone-treated gate-all-around (GAA) devices achieve an outstanding sub-threshold swing (S.S.) of 64 mV/dec at L = 150 nm, approaching the theoretical limit, and exhibit an Ion/Ioff ratio exceeding 1.44×10⁸. The ozone IL treatment significantly reduces oxygen vacancy (V_O) concentration, enhancing channel integrity, electrostatic control, reliability, scalability, and subthreshold swing precision. This metal interlayer significantly reduces source/drain contact resistance, resulting in a 2.3× performance enhancement for three-tier devices compared to single-tier counterparts. These combined advancements underscore the potential of IGZO GAA structures for next-generation high-performance semiconductor applications.

The improvement in electrical properties of bottom-gate AlO $_{\textit{x}}$ -passivated 1.8-nm-thick InO $_{\textit{x}}$ FETs by inserting a 1.1-nm thick AlO $_{\textit{x}}$ interlayer between the oxide channel and HfO $_{\textit{x}}$ dielectric is experimentally investigated. The ultrathin AlO $_{\textit{x}}$ interlayer prevents impurities diffusion from the HfO $_{\textit{x}}$ layer into InO $_{\textit{x}}$ channels during fabrication, which can address the negative initial ${V}_{\text {th}}$ issue in devices with single-HfO $_{\textit{x}}$ dielectric. The InO $_{\textit{x}}$ FETs with AlO $_{\textit{x}}$ /HfO $_{\textit{x}}$ dielectric provide a positive threshold voltage ( ${V}_{\text {th}}\text {)}$ of 0.22V and the subthreshold swing (SS) of 65.8 mV/dec after annealing in N₂ ambient at $300~^{\circ }$ C. Due to the reduction of interface trap density and the number of fixed charges by an ultrathin AlO $_{\textit{x}}$ interlayer, devices with $300~^{\boldsymbol {\circ }}$ C annealing show excellent positive and negative bias instability of 52 and 58 mV for 3-h stressing at a ${V}_{\text {g}}-{V}_{\text {th}}$ of $\boldsymbol {\vert }{{1}}{\,}\text{V} \boldsymbol {\vert }$ , respectively. Finally, the possible mechanisms of bias stress instability in InO $_{\textit{x}}$ FETs with AlO $_{\textit{x}}$ /HfO $_{\textit{x}}$ dielectric are discussed.

In this work, we experimentally demonstrate a high-mobility Ge Complementary FET (CFET) fabricated by a wafer bonding technique. CMOS-friendly manufacturing processes, including vacuum annealing and TMAH-based etching solutions, have been developed to acquire high-quality suspended Ge channels. Significant improvement of surface roughness by at least 64% and elimination of mismatch dislocation of Ge nanosheets generated during Ge/Si epitaxial growth has been achieved. The suspended Ge channels exhibit nearly defect-free quality, leading to high-performance vertically stacked 3-layer pFET/3-layer nFET nanosheet (P-3NS/N-3NS) Ge CFET. Well-behaved Ge nanosheet p/nFETs performance and excellent voltage transfer characteristics (VTC) behaviors of Ge CFET inverters have been successfully demonstrated.

For high-performance p-type field-effect transistors (FETs) based on two-dimensional (2D) materials, the use of Pt as the contact metal, with its high work function, is advantageous for effective hole injection into the 2D channel. However, the high-energy sputtering process required to deposit Pt, due to its high melting point, often induces significant damage to the 2D materials. Recently, the achievement of nearly ideal van der Waals contacts in Sb₂Te₃/MoS₂ via sputtering has motivated us to investigate WSe₂ p-FETs with sputtered Pt electrodes. Notably, reasonable p-FET performance was observed even in monolayer WSe₂. However, various characterizations revealed that the crystal structure of WSe₂ was no longer preserved, suggesting the formation of a quasi-edge contact between Pt-sputtered WSe₂ and the WSe₂ channel. Moreover, from the perspective of sputtering applicability, the relationship between deposition methods, deposited materials, and the resulting extent of damage was systematically examined.

The role of excess oxygen in oxide-semiconductor channel in electrical and bias instability characteristics of AlOx-passivated ultrathin InOx FETs fabricated by plasma-enhanced atomic layer deposition is systematically studied with different channel thickness. The acceptor-like traps induced from excess oxygen, incorporated during deposition process or oxidizing annealing, degrades the instability in ultra-thin 1.8 nm InOx. Although annealing in N2 ambient can relieve the excess oxygen issue in a thin channel, it will lead to hump behavior due to the generation of inhomogeneous channel in a thicker InOx channel. While mobility increases in AlOx/InOx FETs after N2 annealing, a reduction is observed after O2 annealing at a same channel thickness due to a stronger scattering from traps. Afterall, it is still considered that using a thicker channel of 2.6 nm annealed by O2 ambient will be a better strategy for applying InOx channel into BEOL-transistors, from the perspective of Vth value (-1.2 V), mobility (32.1 cm2/Vs) and PBS instability (48 mV for 1-hour).

The high Schottky barrier height (SBH) of p-type germanium (Ge) with highly conductive Cerium(Ce)-doped hydrogenated indium oxide (ICO:H) has been investigated through temperature-dependent capacitance-voltage (C-V) and current-voltage(I-V) characteristics. The reverse bias C-V measurements revealed that the SBH is 0.412 eV at 300 K, indicating Fermi-level de-pinning. As the temperature decreased to 80 K, the SBH increases to 0.471 eV. Using the thermal emission theory of the forward I-V characteristic, the zero-bias SBH decreases from 0.494 eV at 300 K to 0.263 eV at 80 K. This variation is well explained by considering a Gaussian distribution of the SBH. From the modified Richardson plot, we obtained the Richardson constant (A ${}^{\boldsymbol {\ast }}$ ) of 41.6 Acm ${}^{\mathbf {-{2}}}$ K ${}^{\mathbf {-{2}}}$ , which is extremely close to the theoretical value of 40.8 Acm ${}^{\mathbf {-{2}}}$ K ${}^{\mathbf {-{2}}}$ for holes in p-type Ge, suggesting ICO:H/p-Ge interface exhibits fairly ideal Schottky barrier behavior.

The feasibility of Bi2Te3 as S/D contact for n-Ge has been investigated. After thermal treatment at 400 °C, the formation of Ge1−xBi2+xTe4 (GBT) ternary compound and the realization of the quasi-van der Waals interface are verified from x-ray diffraction analysis and scanning transmission electron microscope observation at the GBT/Ge interface. According to the junction diode characteristics of GBT/Ge, exhibiting Ohmic and rectified behaviors on n-Ge and p-Ge, respectively, it is found that strong Fermi-level pinning commonly observed between metal and n-Ge is mitigated and the Fermi level of Ge moves toward the conduction band side. In addition, the interfacial layer between GBT and Ge even disappeared after 400 °C annealing, leading to ideal Ohmic behavior compared to its Bi2Te3 counterpart. GBT/Ge hetero-structure possesses high thermal stability, which shows tolerance for the back-end-of-the-line process. Through the comprehensive evaluation, GBT shows exceptional potential for achieving low contact resistance in Ge nMOSFETs.