Daniel Nagy

The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current (IDD) because the gate scaling to 10 nm results in a decline of the current (by 10.7%). IDD of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches 1×1020cm-3, or increase by 3.8% if the high-κ dielectric layer equivalent oxide thickness (EOT) is less than 1.0 nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. IDD will increase by 3% and by 14% in the 10 nm gate NS FET with the 110and 100channel orientations, respectively, when a strain of 0.5% is applied to the channel, with a negligible increase for larger strain values (0.7% and 1.0%).

The beneficial characteristics of polyoxometalate (POM) molecule-based flash memory cells provide interesting opportunities for scaling beyond the limitations of conventional flash cells. In this paper, we study the write, erase, and retention times of POM flash cells using a kinetic Monte Carlo method implemented in the multi-scale Nano-Electronic Simulation Software simulation framework. The POM flash structure is optimized by studying the tradeoffs between program/erase time and retention time. Based on the optimized POM flash structure, the POM molecular layer charging and discharging processes as well as the corresponding threshold voltage variation are analyzed. The distributions of write, erase, and retention times are simulated and analyzed when studying the POM flash dynamic charging and discharging characteristics.

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.

The modelling of conventional and novel memory devices has gained significant traction in recent years. This is primarily because the need to store increasingly larger amount of data demands a better understanding of the working of the novel memory devices, to enable faster development of the future technology generations. Furthermore, in-memory computing is also of great interest from the computational perspectives, to overcome the data transfer bottleneck that is prevalent in the von-Neumann architecture. These important factors necessitates the development of comprehensive TCAD simulation tools that can be used for modeling carrier dynamics in the gate oxides of the Flash type memory cells. In this work, we introduce the kinetic Monte Carlo module that we have developed and integrated within the Nano Electronic Simulation Software (NESS) - to model electronic charge transport in Flash memory type structures. Using the developed module, we perform retention time analysis for a polyoxometalate (POM) molecule-based charge trap flash memory. Our simulation study highlights that retention characteristics for the POM molecules has a unique features that depends on the properties of the tunneling oxide.

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (LG) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current (ION) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (IOFF), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gateall-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation (σ) for the threshold voltage (V _T ) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, σV _T due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD (σV _T,comb ) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET.

Variability of semiconductor devices is seriously limiting their performance at nanoscale. The impact of variability can be accurately and effectively predicted by computer aided simulations in order to aid future device designs. Quantum corrected (QC) drift-diffusion (DD) simulations are usually employed to estimate the variability of state-of-the-art non-planar devices but require meticulous calibration. More accurate simulation methods, such as QC Monte Carlo (MC), are considered time consuming and elaborate. Therefore, we predict TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability on a 10 nm gate length gate-all-around Si nanowire FET and perform a rigorous comparison of the QC DD and MC results. In case of the MGG, we have found that the QC DD predicted variability can have a difference up to 20 % in comparison with the QC MC predicted one. In case of the LER, we demonstrate that the QC DD can overestimate the QC MC simulation produced variability by a significant error of up to 56 %. This error between the simulation methods will vary with the root mean square (RMS) height and maximum source/drain n-type doping. Our results indicate that the aforementioned QC DD simulation technique yields inaccurate results for the ON-current variability.