David Declercq

This paper proposes a new finite precision iterative decoder for low-density parity-check (LDPC) codes. The proposed decoder, named Sign-Preserving Min-Sum (SP-MS), significantly improves the decoding performance compared to the classical Offset Min-Sum (OMS) decoder when messages are quantized on q = 2, 3, or 4 bits. The particularity of the SP-MS decoder is that messages cannot take the 0 value, and can fully benefit from the q bits of precision. The optimization of the SP-MS decoder is investigated in the asymptotic limit of the code length using density evolution (DE). Our study shows that 3-bit SP-MS decoders can achieve the same error-correcting performance as 5-bit OMS decoders, and 2-bit SP-MS decoders outperform 3-bit OMS decoders. The finite-length simulations confirm the conclusions of the DE analysis for several LDPC codes. Our SP-MS decoder shows a signal-to-noise ratio (SNR) gain up to 0.43 dB, with a memory/wire reduction of up to 40%, compared to the OMS decoder. Moreover, the SP-MS decoder converges faster and uses fewer iterations than the OMS decoder, with an improvement of up to 83.3% of the average decoding throughput. On an FPGA, the SP-MS decoder reduces resource utilization by up to 56% compared to the OMS decoder.

Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design.

Since the degree-1 variable nodes (VNs) in the low-density parity-check (LDPC) codes for the 5th generation (5G) mobile communications are very sensitive to be erroneous, the quantized min-sum (QMS) and offset min-sum (QOMS) decodings suffer from poor error-correction performance due to the imprecise estimation of the check-to-variable (C2V) message magnitudes. For this reason, this paper proposes a decomposition mapping based quantized belief propagation (DM-QBP) decoding for 5G LDPC codes. In order to reduce the computation complexity, the check node (CN) update function is realized by look-up tables (LUTs). Furthermore, a decomposition method is presented to eliminate the high memory cost of using large tables without performance loss. Therefore, the CN update function can be implemented based only on simple mappings and fixed-point additions. Simulation results show that, the DM-QBP decoder considerably outperforms the state-of-the-art ones for several 5G LDPC codes. With a small number of quantization bits, its performance is even better than the floating-point OMS decoding in some cases.

Systematic Polar codes offers the same frame-error-rate (FER) performance compared with non-systematic Polar codes in almost communications channels although they have advantages in bit-error-rate (BER) performance. In recent papers, NAND flash memories have been confirmed for its asymmetric error characteristic, and the 2-Beta-Binomial (2-BBM) error model has been presented to provide accurate simulation of observed errors in multi-level cell (MLC) flash memories under different Program/Erase cycles. In this paper, we propose concatenating a distribution generator (DG) which can modify user data distribution with systematic Polar encoder (SPE) for MLC NAND Flash memory. The proposed method shows remarkable improvement in FER performances compared with non-systematic candidates, especially in lower pages of the two memory vendors.

We propose in this paper a new approach of applying the Non-Surjective Finite Alphabet Iterative Decoder (NS-FAID) for the Low-Density Parity-Check (LDPC) decoding. Differently from the NS-FAID which applies a fixed nonlinear function by using a fixed Look-Up-Table (LUT) on the variable node messages, the proposed method, called Probabilistic FAID (PFAID), uses more than one LUT in a probabilistic way. By using the density evolution, we show that this method provides a significant improvement in performance compared to the NS-FAID and the traditional MS. The advantage of PFAID is shown by the fact that, a PFAID with low message quantization level can reach or even surpass the performance of the higher level quantization MS decoder. Furthermore, we show that PFAID can be efficiently implemented with no hardware overhead compared to Min-Sum (MS) or NS-FAID with the same message quantization level. The hardware complexity analysis and decoding simulation performance are provided as superiority evidences of PFAID over the referenced benchmarks.

This paper proposes a holistic approach that addresses both the message mapping in memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) decoders. We consider a layered hardware architecture using single read/single write port memory banks. The throughput of such an architecture is limited by memory access conflicts, due to improper message mapping in the memory banks, and by pipeline data hazards, due to delayed update effect. We solve these issues by: 1) a residue-based layered scheduling that reduces the pipeline related hazards and 2) off-line algorithms for optimizing the message mapping in memory banks and the message read access scheduling. Our estimates for different LDPC codes indicate that the hardware usage efficiency of our layered decoder is improved by 3%-49% when only the off-line algorithms are employed and by 16%-57% when both the residue-based layered architecture and the off-line algorithms are used.

This paper presents a new bit flipping (BF) decoder, called the probabilistic parallel BF (PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to significantly improve the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in Section II. The application-specific integrated circuit synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.

This paper investigates a new approach to decoding (higher order) multi-level polar coded modulations (MLCM). In general MLCM, bit-levels are encoded and decoded separately, thus leading to a delicate “rate-allocation” task. In this paper, we show that the structure of Successive Cancellation (SC)-based polar decoders, such as SC-List or SC-Flip, can be efficiently exploited to improve the decoding performance. Instead of considering each bit-level separately, the proposed lasting decoders work continuously along all the bit-levels. At the cost of a slight increase of the complexity, these decoders offer significantly better performance, and make the rate-allocation problem very simple. Finally, it is shown that multi-level polar coded modulations offer a clear advantage as compared to bit-interleaved polar coded modulations.

This paper proposes a generalization of the recently introduced successive cancellation flip (SCFlip) decoding of polar codes, characterized by a number of extra decoding attempts, where one or several positions are flipped from the standard SC decoding. To make such an approach effective, we first introduce the concept of higher order bit flips and propose a new metric to determine the bit flips that are more likely to correct the trajectory of the SC decoding. We then propose a generalized SCFlip decoding algorithm, referred to as dynamic-SCFlip (D-SCFlip), which dynamically builds a list of candidate bit flips, while guaranteeing that the next attempt has the highest probability of success among the remaining ones. Simulation results show that D-SCFlip is an effective alternative to SC-list decoding of polar codes, by providing very good error correcting performance, with an average computation complexity close to the one of the SC decoder.

The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder offers a significant improvement in decoding performance for Low-Density Parity-Check (LDPC) codes on Binary Symmetric Channel (BSC). However, this outstanding decoding performance comes along with a non-negligible extra hardware cost to realize the probabilistic behavior on top of the deterministic Gradient Descent Bit-Flipping (GDBF) decoder. This paper presents a novel solution to implement PGDBF decoder on Quasi-Cyclic LDPC codes. The proposed architecture takes advantage of the cyclic shift permutation nature of QC-LDPC and changes the message flow such that a probabilistic behavior is emulated without the cost of an actual probabilistic signal generator. It is shown that, the proposed architecture improves the PGDBF decoding performance with respect to the state-of-the-art implementation while reducing hardware complexity, even being lower than that of the deterministic GDBF. The efficiency of our proposed method is verified through the ASIC 90nm CMOS technology implementations and decoding simulations.