Alessandro Biondi
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Alessandro Biondi has a total of 105 co-authors. Here are the top co-authors by number of shared publications:
- Giorgio Buttazzo
Scuola Superiore Sant’Anna
23 shared publications - Giulio Rossolini
Dept. of Excellence in Robotics & AI, Scuola Superiore Sant'Anna, Pisa, Italy
10 shared publications - Daniel Casini
Sant’Anna School of Advanced Studies, Pisa, Italy
9 shared publications - Fabio Brau
Scuola Superiore Sant'Anna
6 shared publications - Federico Nesti
Department of Excellence in Robotics and AI, Scuola Superiore SantAnna, Pisa, Italy
5 shared publications - Francesco Restuccia
University of California San Diego
5 shared publications
Latest Publications
- Open Access
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 6136-6150
Branch Target Reuse: Practical Spectre-v2 Attacks in JIT Engines via Stale Branch Prediction Entries
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 6136-6150
Open AccessBranch Target Reuse: Practical Spectre-v2 Attacks in JIT Engines via Stale Branch Prediction Entries
- Open Access
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 67-78
Position Matters: Feature Inversion Attacks in ViT Split Inference with Token Reduction and Shuffling
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 67-78
Open AccessPosition Matters: Feature Inversion Attacks in ViT Split Inference with Token Reduction and Shuffling
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Information Forensics and Security
- Vol. 21, 7890-7903
Edge-Only Universal Adversarial Attacks in Distributed Learning
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Information Forensics and Security
- Vol. 21, 7890-7903
Edge-Only Universal Adversarial Attacks in Distributed Learning
- Open Access
- 17 December 2025
- Published by Elsevier in Internet of Things
- Vol. 36
End-To-end response-time analysis of DDS-based real-time applications
- 17 December 2025
- Published by Elsevier in Internet of Things
- Vol. 36
Open AccessEnd-To-end response-time analysis of DDS-based real-time applications
- 10 October 2025
- Published by Elsevier in Internet of Things
- Vol. 34
Exploiting edge features for transferable adversarial attacks in distributed machine learning
- 10 October 2025
- Published by Elsevier in Internet of Things
- Vol. 34
Exploiting edge features for transferable adversarial attacks in distributed machine learning
- 8 September 2025
- Published by Elsevier in Pattern Recognition
- Vol. 172
Benchmarking the spatial robustness of DNNs via natural and adversarial localized corruptions
- 8 September 2025
- Published by Elsevier in Pattern Recognition
- Vol. 172
Benchmarking the spatial robustness of DNNs via natural and adversarial localized corruptions
- 22 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 72 (11) , 1625-1629
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Next-generation mixed-criticality Systems-on-chip (SoCs)for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges,in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm.
- 22 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 72 (11) , 1625-1629
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Next-generation mixed-criticality Systems-on-chip (SoCs)for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges,in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm.
- 8 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 74 (9) , 3072-3086
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
The automotive industry is transitioning from federated, homogeneous, interconnected devices to integrated, heterogeneous, mixed-criticality systems (MCS). This leads to challenges in achieving timing predictability techniques due to access contention on shared resources, which can be mitigated using hardware-based spatial and temporal isolation techniques. Focusing on the interconnect as the point of access for shared resources, we propose AXI-REALM, a lightweight, modular, technology-independent, and open-source real-time extension to AXI4 interconnects. AXI-REALM uses a budget-based mechanism enforced on periodic time windows and transfer fragmentation to provide fair arbitration, coupled with execution predictability on real-time workloads. AXI-REALM features a comprehensive bandwidth and latency monitor at both the ingress and egress of the interconnect system. Latency information is also used to detect and reset malfunctioning subordinates, preventing missed deadlines. We provide a detailed cost assessment in a$12\,$ nm node and an end-to-end case study implementing AXI-REALM into an open-source MCS, incurring an area overhead of less than$2\,\%$ . When running a mixed-criticality workload, with a time-critical application sharing the interconnect with non-critical applications, we demonstrate that the critical application can achieve up to$68.2\,\%$ of the isolated performance by enforcing fairness on the interconnect traffic through burst fragmentation, thus reducing the subordinate access latency by up to 24 times. Near-ideal performance, (above$95\,\%$ of the isolated performance) can be achieved by distributing the available bandwidth in favor of the critical application.- 8 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 74 (9) , 3072-3086
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
The automotive industry is transitioning from federated, homogeneous, interconnected devices to integrated, heterogeneous, mixed-criticality systems (MCS). This leads to challenges in achieving timing predictability techniques due to access contention on shared resources, which can be mitigated using hardware-based spatial and temporal isolation techniques. Focusing on the interconnect as the point of access for shared resources, we propose AXI-REALM, a lightweight, modular, technology-independent, and open-source real-time extension to AXI4 interconnects. AXI-REALM uses a budget-based mechanism enforced on periodic time windows and transfer fragmentation to provide fair arbitration, coupled with execution predictability on real-time workloads. AXI-REALM features a comprehensive bandwidth and latency monitor at both the ingress and egress of the interconnect system. Latency information is also used to detect and reset malfunctioning subordinates, preventing missed deadlines. We provide a detailed cost assessment in a$12\,$ nm node and an end-to-end case study implementing AXI-REALM into an open-source MCS, incurring an area overhead of less than$2\,\%$ . When running a mixed-criticality workload, with a time-critical application sharing the interconnect with non-critical applications, we demonstrate that the critical application can achieve up to$68.2\,\%$ of the isolated performance by enforcing fairness on the interconnect traffic through burst fragmentation, thus reducing the subordinate access latency by up to 24 times. Near-ideal performance, (above$95\,\%$ of the isolated performance) can be achieved by distributing the available bandwidth in favor of the critical application.- Open Access
- 6 May 2025
- Published by Association for Computing Machinery (ACM)
- p. 1-2
Integrating the Simplex Architecture to Enhance Safety in Deep Learning Autonomous Systems
- 6 May 2025
- Published by Association for Computing Machinery (ACM)
- p. 1-2
Open AccessIntegrating the Simplex Architecture to Enhance Safety in Deep Learning Autonomous Systems
- 10 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Dependable and Secure Computing
- Vol. 22 (5) , 4580-4592
Hazardous Behavior Analysis for Complex Pre-Existing Software in Safety-Critical Context: Approach and Application to the Linux Dynamic Memory Allocator
As system designers are transitioning to the usage of pre-existing software architectural elements to reduce time-to-market and costs, they face challenges in safety-critical applications. Pre-existing software may have been implemented without following any safety and/or quality standard, and its documentation may be incomplete or unclear. As recommended by part 6 of the functional safety standard ISO 26262 (product development at the software level), stringent rules and guidelines must be followed during the implementation of a new software. The qualification of a pre-existing software according to ISO 26262 may hence be very time consuming and expensive if not addressed in a structured way. This work presents STPA for Pre-existing Software (STPA-PES), a new software hazardous behavior analysis approach designed to identify criticalities or abnormal conditions in complex pre-existing software to be mitigated with adequate safety measures. The major challenge in such a process consists in the definition of a model that correctly represents the system under analysis when the architectural design of pre-existing software is not available. As a relevant example, the proposed approach is finally applied to dynamic memory allocator (DynMA) in Linux kernel to show how STPA-PES is able to derive safety requirements of this software architectural element.
- 10 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Dependable and Secure Computing
- Vol. 22 (5) , 4580-4592
Hazardous Behavior Analysis for Complex Pre-Existing Software in Safety-Critical Context: Approach and Application to the Linux Dynamic Memory Allocator
As system designers are transitioning to the usage of pre-existing software architectural elements to reduce time-to-market and costs, they face challenges in safety-critical applications. Pre-existing software may have been implemented without following any safety and/or quality standard, and its documentation may be incomplete or unclear. As recommended by part 6 of the functional safety standard ISO 26262 (product development at the software level), stringent rules and guidelines must be followed during the implementation of a new software. The qualification of a pre-existing software according to ISO 26262 may hence be very time consuming and expensive if not addressed in a structured way. This work presents STPA for Pre-existing Software (STPA-PES), a new software hazardous behavior analysis approach designed to identify criticalities or abnormal conditions in complex pre-existing software to be mitigated with adequate safety measures. The major challenge in such a process consists in the definition of a model that correctly represents the system under analysis when the architectural design of pre-existing software is not available. As a relevant example, the proposed approach is finally applied to dynamic memory allocator (DynMA) in Linux kernel to show how STPA-PES is able to derive safety requirements of this software architectural element.