Kyung Min Kim

As conventional digital computing becomes increasingly constrained by scalability and energy‐efficiency limits, computing based on intrinsic physical dynamics of devices has emerged as a promising alternative. In this context, three‐terminal devices have attracted attention because their additional terminal offers greater flexibility for implementing higher‐order dynamics than two‐terminal devices. Here, we present a dual‐state programmable oxide transistor (DUPOT) that exhibits a previously unreported form of high‐dimensional dynamical behavior with both the threshold voltage ( V _th ) and the saturation current ( I _sat ) independently tunable. Additionally, the programmed V _th state exhibits long‐term memory (LTM) characteristics, whereas the I _sat state shows short‐term memory (STM) behavior, enabling more complex computing functionalities. We elucidate its operating mechanisms and demonstrate robustness, and further showcase its use in time‐based cryptography, which fully exploits its rich dynamical behavior. Our array‐level demonstration supports diverse forms of time‐based cryptography, including time‐release encryption and time‐bound encryption, and can be extended to cloud cryptographic systems, marking a new milestone in the study of computing devices with higher‐order dynamics.

Memristors exhibit tunable resistance, which has been widely exploited in non‐volatile memory, in‐memory computing, and neuromorphic computing. They can also serve as an entropy source due to their inherent instability, making them attractive for security devices and probabilistic computing. When these two characteristics are coupled, memristors can act as tunable entropy sources; however, this direction remains largely unexplored. Here, we propose a spiking‐rate‐programmable probabilistic neuron that leverages the tunable noise characteristics of a Ru/TaO _x /Pt memristor. In this memristor, the conduction mechanism varies across resistance states, leading to distinct noise behaviors and signal‐to‐noise ratios that depend on the programmed resistance. This noise can be harnessed to realize frequency‐selective, frequency‐domain probabilistic neural encoding. By integrating these probabilistic neurons, an identical network architecture can process input signals spanning a wide frequency range, achieving around 95% classification performance on both low‐frequency human activity data (UCI HAR, 0.4–25 Hz) and high‐frequency speech data (Audio MNIST, 20 Hz–8 kHz). These results highlight a new direction that leverages the intrinsic properties of memristors for compact, adaptive, and energy‐efficient time‐series encoding.

Probabilistic computing is an emerging approach for solving combinatorial optimization and probabilistic inference by leveraging stochastic dynamics to explore complex energy landscapes. However, most hardware implementations remain constrained to binary probabilistic bits (p‐bits), limiting efficiency for inherently multi‐class problems. Here, we propose and experimentally demonstrate a ternary Potts machine (TPM) enabled by a NbO _x oscillator‐based probabilistic ternary digit unit (i.e., p‐trits). The p‐trit exploits electro‐thermal dynamics of a NbO _x threshold‐switching memristor that exhibits two distinct negative differential resistance regimes, producing stochastic transitions among three discrete states (off/osc/on). A compact p‐trit circuit digitizes the oscillatory signals into two‐bit outputs, yielding a practical p‐trit with an operation rate of 2.5 µs/bit, while the NbO _x oscillator, which is the primary source of energy consumption, consumes 2.4 nJ/bit. A microcontroller unit ‐integrated TPM prototype solves Max‐3‐Cut with ∼30% higher accuracy than p‐bit‐based computing while requiring ∼33% of its computational overhead. Simulations on the weighted ternary number partitioning problem confirm scalability and robustness, showing convergence of up to 99.96%, comparable to near‐optimal solutions.

In‐sensor processing is a key enabler for edge computing because it allows sensor data to be processed locally, thereby reducing data movement and improving the efficiency of complex workloads. In particular, emerging computationally intensive applications such as explainable artificial intelligence (XAI) further increase the demand for dedicated in‐sensor hardware capable of efficient sensor‐level processing. Here, we report an optoelectronic memtransistor (OEMT) that integrates a photoresponsive indium zinc oxide (IZO) channel with a NbO _x /AlO _x charge‐trapping gate stack, enabling optical sensing, electrical masking, and non‐volatile memory within a single three‐terminal device architecture. We experimentally demonstrate sensor‐level vision explainable artificial intelligence (VXAI) operation using a 3 × 3 OEMT array and validate its scalability through hardware‐based simulations. Compared with a conventional sensing–processing pipeline, the OEMT‐based framework achieves a 21‐fold improvement in system‐level energy efficiency, highlighting its strong potential for efficient sensor‐level processing.

Compressed sensing (CS) enables efficient data acquisition and implicit encryption; however, its recovery stage remains a significant computational bottleneck, as it requires solving large-scale optimization problems by running iterative reconstruction algorithms. Here, we propose an event-driven CS recovery framework developed through an algorithm-hardware co-design approach. This framework employs memristor crossbar array (MCA)-based analog matrix computing (AMC) circuits as the hardware platform and incorporates an efficient CS recovery algorithm (named constrained gradient descent (CGD) algorithm) designed to leverage them. Furthermore, the framework supports event-driven selective recovery via MCA-based feature detection. We fabricated the hardware to validate the proposed framework, and the experimental results demonstrate 20.4× to 45.22× improvements in energy efficiency over state-of-the-art methods for image and ECG signal processing. These results underscore the potential of the proposed framework as a competitive hardware solution for real-time sensing signal processing in edge devices.

Valence change memory (VCM)‐based memristors have emerged as promising artificial synapses for neuromorphic computing, yet their nonlinear conductance modulation and limited endurance remain major bottlenecks. Here, we introduce the baffle system concept into HfO ₂ ‐based VCM memristors to regulate oxygen vacancy (V _O ) transport and improve both synaptic linearity and cycling reliability. Guided by a multiscale simulation framework that integrates density functional theory calculations and finite element method‐based multiphysics modeling, dual Al ₂ O ₃ interlayers were strategically incorporated as nanoscale barriers within the HfO ₂ matrix to modulate V _O migration. The appropriately engineered baffle barriers promote lateral filament growth, enhancing synaptic linearity by up to 43%, while simultaneously confining V _O s to achieve over a 60× improvement in endurance. The proposed memristive baffle system provides a practical materials design strategy for precise control of ion transport and filament dynamics, contributing to the development of advanced memristive materials and enhancing their feasibility for neuromorphic applications.

Many electrochemical biosensors operate based on a threshold-sensing (TS) method, which indicates the presence of a disease when the concentration of a biomarker exceeds a predetermined, disease-specific threshold. The TS in biosensor systems is often implemented using power-hungry signal processing (SP) modules or computers, which increases energy consumption and system complexity. Here, we propose a memristor-based bio-to-electrical transducer with built-in TS functionality, allowing TS to be performed directly within the transducer instead of relying on SP modules and computers. Fabricated resistive random-access memory-based TaO _X /Ta ₂ O ₅ memristors meet the transducer requirements, such as a high on/off ratio greater than 30 while maintaining a long unit pulse width exceeding 10 μs. The intended operation of the proposed transducer was experimentally confirmed by the immediate change in resistance of the memristor (R _M ) from high resistance state to low resistance state. Using this proposed transducer, a complete electrochemical biosensor system was implemented by integrating a sensor electrode for pH sensing, an SP module, and a display with the proposed transducer. The memristor-based system offers flexible control of the threshold pH point through a simple design, making it well-suited for point-of-care diagnostics, where portability is highly essential.

Understanding the mechanisms of domain nucleation and growth in ferroelectric materials is essential for developing faster ferroelectric memory devices. In this work, we combine domain imaging using piezoresponse force microscopy (PFM) with a pulse switching method to investigate the origin and evolution of ferroelectric domain nucleation in polycrystalline Pb(Zr52Ti48)O3-based ferroelectric capacitors. PFM imaging revealed that domain reversal is highly dependent on the voltage sweep direction, with forward sweeps achieving complete polarization reversal within a wider voltage range when compared to reverse sweeps. Interestingly, domain nucleation predominantly occurs at grain boundaries, which not only serve as initiation sites but also restrict the expansion of switched domains, thereby impacting switching uniformity and kinetics. To further quantify the polarization-switching kinetics, we employed the pulse switching method and fitted the resulting data with the nucleation-limited switching (NLS) model. The extracted parameters, including the activation field of 8.35 MV/m, the intrinsic switching time of 0.40 μs, and the width of switching time distribution, support PFM results indicating that nucleation is the rate-limiting step in the switching process of these polycrystalline films. In addition, the distribution width of switching times narrowed with increasing electric field, showing enhanced uniformity in domain nucleation under higher field strengths. These findings emphasize the significance of grain boundary-mediated nucleation in polycrystalline PZT films and underscore the effectiveness of the NLS model for understanding and optimizing ferroelectric switching performance. This study paves the way for engineering grain boundaries and minimizing defect-related barriers to achieve more uniform and efficient domain switching in ferroelectric devices.

Hybrid bonding, referring to direct bonding between metal and insulator layers, has become a key technology for next‐generation semiconductor packaging, enabling high‐density interconnects, fast signal transmission, and a compact form factor. Polymer dielectrics such as benzocyclobutene (BCB) provide excellent insulation and adhesion but pose challenges for chemical mechanical polishing (CMP) due to their viscoelasticity. Here, a CMP‐compatible strategy based on argon (Ar) plasma modification of BCB is proposed to enable effective planarization of Cu/BCB hybrid bonding interfaces. Ar plasma treatment increases surface hardness and brittleness of half‐cured BCB and increases hydrophilicity. The resulting wrinkle structures improve the flow of abrasive particles and slurry, enabling a plowing‐dominant removal mechanism for precision planarization. Modified BCB shows a removal rate of up to 17.3 nm s ⁻¹ , over five times higher than untreated BCB, while Cu surface roughness is reduced from 51.4 to 3.0 nm. A time‐dependent dishing model is developed to elucidate dishing mechanism and to control dishing geometry precisely. Using this model, a BCB dishing depth of 230 nm is achieved, supporting void‐free and reliable hybrid bonding. Overall, this study presents a simple yet practical approach to CMP of soft polymer dielectrics and offers a promising solution to advanced heterogeneous integration technologies.

Charge trap memristors (CTM) are promising candidates for nonvolatile analog units in crossbar array platforms, offering a pathway to next‐generation high‐density memory and synaptic arrays, due to their low‐current operation and self‐rectifying characteristics. However, the charge trapping process is inherently slow, posing a significant challenge to achieving high‐speed operation. In this study, a CTM device incorporating a gold nanoparticle (Au NP) layer, referred to as NP‐CTM, is proposed. This design improves programming speed by a factor of ≈47.6, while maintaining excellent stability and retention characteristics. These enhancements are attributed to the synergistic effects of enhanced electric fields and an engineered band structure, both achieved through the physical structure and material properties of Au NPs. The findings are validated through multiphysics‐based simulations and conduction band model analyses. The improved speed and the resulting reduction in programming energy of the CTM device make it a promising candidate for large‐scale applications.