Rende Zhao
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Rende Zhao has a total of 69 co-authors. Here are the top co-authors by number of shared publications:
- Qingzeng Yan
College of New Energy, China University of Petroleum (East China), Qingdao, China
22 shared publications - Hailiang Xu
College of New Energy, China University of Petroleum (East China), Qingdao, China
17 shared publications - Jinkui He
College of New Energy, China University of Petroleum (East China), Qingdao, China
9 shared publications - Xibo Yuan
China University of Mining and Technology
9 shared publications - Qingxiao Du
College of New Energy, China University of Petroleum (East China), Qingdao, China
6 shared publications - Cun Wang
Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada
5 shared publications
Latest Publications
- 1 October 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 73  (10) , 15553-15558
Novel Dynamic Amplitude Normalization Method Based on Tracking Differentiator for SOGI-FLL
- 1 October 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 73  (10) , 15553-15558
Novel Dynamic Amplitude Normalization Method Based on Tracking Differentiator for SOGI-FLL
- 2 September 2026
- Published by Springer Nature
- p. 312-323
Linear Active Disturbance Rejection Control for Enhanced Sub-Synchronous Oscillation Suppression in DFIG Wind Power System
- 2 September 2026
- Published by Springer Nature
- p. 312-323
Linear Active Disturbance Rejection Control for Enhanced Sub-Synchronous Oscillation Suppression in DFIG Wind Power System
- Open Access
- 1 September 2026
- Published by MDPI AG in Nanomaterials
- Vol. 16  (17) , 1091
High-Performance Hydrogen Sensor Fabricated by Layer-by-Layer Self-Assembly for Real-Time Monitoring of Hydrogen Production by Water Electrolysis
In this study, ZnO/Co3O4 composite thin-film room-temperature hydrogen (H2) sensors were prepared via the hydrothermal method and self-assembly techniques. The test results show that the composite sensor with a layer assembly ratio of 1:1 has good sensing performance for H2. The ZnO/Co3O4 composite sensor can detect a wide range of H2 concentrations from 100 to 50,000 ppm, and the response toward 300 ppm H2 is more than six-times that of a single nanomaterial. In addition, it has a faster response recovery speed, better repeatability, selectivity and long-term stability. The improvement in composite sensor performance results from the synergistic effect between ZnO and Co3O4 materials and the formation of heterostructures. The prepared ZnO/Co3O4 composite thin-film sensor was successfully applied to detect the H2 production concentration and behavior of an electrolytic cell for hydrogen production by water electrolysis.
- 1 September 2026
- Published by MDPI AG in Nanomaterials
- Vol. 16  (17) , 1091
Open AccessHigh-Performance Hydrogen Sensor Fabricated by Layer-by-Layer Self-Assembly for Real-Time Monitoring of Hydrogen Production by Water Electrolysis
In this study, ZnO/Co3O4 composite thin-film room-temperature hydrogen (H2) sensors were prepared via the hydrothermal method and self-assembly techniques. The test results show that the composite sensor with a layer assembly ratio of 1:1 has good sensing performance for H2. The ZnO/Co3O4 composite sensor can detect a wide range of H2 concentrations from 100 to 50,000 ppm, and the response toward 300 ppm H2 is more than six-times that of a single nanomaterial. In addition, it has a faster response recovery speed, better repeatability, selectivity and long-term stability. The improvement in composite sensor performance results from the synergistic effect between ZnO and Co3O4 materials and the formation of heterostructures. The prepared ZnO/Co3O4 composite thin-film sensor was successfully applied to detect the H2 production concentration and behavior of an electrolytic cell for hydrogen production by water electrolysis.
- 16 December 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41  (6) , 9651-9666
A Double-Modulation-Wave Quasi-Virtual DPWM for Dead-Time-Effect Elimination in Four-Level π-Type Inverters
Addressing issues such as dc-link voltage unbalance and dead-time effect is essential for the wide-spread application of the four-level (4L) π-type inverter. Effective strategies have been proposed for dc-link voltage balancing. However, existing strategies for suppressing the dead-time effect cannot be directly combined with dc-link voltage balancing strategies. In this article, investigations are carried out to both address the dc-link voltage unbalance issue and the dead-time effect of the 4L π-type inverter. First, a quasi-virtual discontinuous pulsewidth modulation (DPWM) for dc-link voltage balancing and its dead-time effect are briefly presented. Then, the overmodulation issue of the conventional dead-time compensation is analyzed based on the quasi-virtual DPWM. Afterward, the dead-time elimination PWM is tried to combine with the quasi-virtual DPWM, which however has a high dependency on current polarities. To further reduce the dependency on current polarities, a new double-modulation-wave quasi-virtual DPWM is proposed, which combines the quasi-virtual DPWM and the double-modulation-wave PWM. Comparative experimental results shown that, the proposed PWM scheme can both achieve dc-link voltage balancing and dead-time effect suppressing for the 4L π-type inverter.
- 16 December 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41  (6) , 9651-9666
A Double-Modulation-Wave Quasi-Virtual DPWM for Dead-Time-Effect Elimination in Four-Level π-Type Inverters
Addressing issues such as dc-link voltage unbalance and dead-time effect is essential for the wide-spread application of the four-level (4L) π-type inverter. Effective strategies have been proposed for dc-link voltage balancing. However, existing strategies for suppressing the dead-time effect cannot be directly combined with dc-link voltage balancing strategies. In this article, investigations are carried out to both address the dc-link voltage unbalance issue and the dead-time effect of the 4L π-type inverter. First, a quasi-virtual discontinuous pulsewidth modulation (DPWM) for dc-link voltage balancing and its dead-time effect are briefly presented. Then, the overmodulation issue of the conventional dead-time compensation is analyzed based on the quasi-virtual DPWM. Afterward, the dead-time elimination PWM is tried to combine with the quasi-virtual DPWM, which however has a high dependency on current polarities. To further reduce the dependency on current polarities, a new double-modulation-wave quasi-virtual DPWM is proposed, which combines the quasi-virtual DPWM and the double-modulation-wave PWM. Comparative experimental results shown that, the proposed PWM scheme can both achieve dc-link voltage balancing and dead-time effect suppressing for the 4L π-type inverter.
- 16 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41  (3) , 3643-3654
A Compensation-Based 3D-SVPWM Strategy Employing Positive and Negative DC-Link Voltages Sampling for Three-Phase Four-Wire Three-Level Converters
Three-phase four-wire three-level (3P4W-3L) converters demonstrate broad application prospects in off-grid systems, while facing complex and variable operating conditions. Under asymmetrical loads, their dc-link neutral-point potential (NPP) exhibits fundamental-frequency oscillation proportional to the load unbalance factor. The adoption of traditional three-dimensional space vector modulation (3D-SVPWM) based on the assumption of balanced positive and negative dc-link voltages leads to substantial output errors during large-amplitude NPP oscillation, ultimately causing three-phase voltage unbalance and elevated total harmonic distortion (THD). Further theoretical analysis confirms that such errors introduce third-harmonic components in the output voltages. A compensation-based 3D-SVPWM strategy employing positive and negative dc-link voltages sampling is proposed in this article, which constructs the 3D space vector diagram based on the real-time sampling values of positive and negative dc-link voltages. Using the real-time positions of basic vectors, subsectors in the vector diagram are optimally redivided and the vector dwell times are calculated accordingly. This strategy effectively suppresses third-harmonic components in the output voltages, ensuring that the system can still output high-quality voltage waveforms even when the NPP oscillates greatly. Finally, the effectiveness of the proposed strategy is verified through comparative experiments, showing a high balance degree and low THD of the output voltages.
- 16 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41  (3) , 3643-3654
A Compensation-Based 3D-SVPWM Strategy Employing Positive and Negative DC-Link Voltages Sampling for Three-Phase Four-Wire Three-Level Converters
Three-phase four-wire three-level (3P4W-3L) converters demonstrate broad application prospects in off-grid systems, while facing complex and variable operating conditions. Under asymmetrical loads, their dc-link neutral-point potential (NPP) exhibits fundamental-frequency oscillation proportional to the load unbalance factor. The adoption of traditional three-dimensional space vector modulation (3D-SVPWM) based on the assumption of balanced positive and negative dc-link voltages leads to substantial output errors during large-amplitude NPP oscillation, ultimately causing three-phase voltage unbalance and elevated total harmonic distortion (THD). Further theoretical analysis confirms that such errors introduce third-harmonic components in the output voltages. A compensation-based 3D-SVPWM strategy employing positive and negative dc-link voltages sampling is proposed in this article, which constructs the 3D space vector diagram based on the real-time sampling values of positive and negative dc-link voltages. Using the real-time positions of basic vectors, subsectors in the vector diagram are optimally redivided and the vector dwell times are calculated accordingly. This strategy effectively suppresses third-harmonic components in the output voltages, ensuring that the system can still output high-quality voltage waveforms even when the NPP oscillates greatly. Finally, the effectiveness of the proposed strategy is verified through comparative experiments, showing a high balance degree and low THD of the output voltages.
- 8 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 73  (1) , 1209-1222
A Quasi-Virtual DPWM Implemented With Split Modulation Waves for DC-Link Voltage Balancing in Four-Level π-Type Inverters
The balance of dc-link voltages is quite a challenge in the four level (4L) π-type inverter, which is the main factor limiting its wide application. In this article, an investigation is conducted to simultaneously balance dc-link voltages and reduce switching losses in 4L π-type inverters. First, the mechanism of the dc-link voltage balancing method based virtual vectors is analyzed, which however will inevitably increase switching losses. To reduce the switching losses, a discontinuous pulse width modulation (DPWM) implemented based on virtual vectors is presented. Then, the vector sequences are rearranged proposing a quasi-virtual DPWM for balancing dc-link voltages of the 4L π-type inverter. And a simplified carrier-based implementation method is introduced with split modulation waves. Auxiliary closed control loops are designed for controlling and balancing dc-link voltages. In addition, the advantage of low common-mode voltage in the quasi-virtual DPWM is analyzed and presented. A three-phase 4L π-type inverter experimental setup is built based on a DSP-FPGA control board. The proposed quasi-virtual DPWM is finally verified by comparative experiments, showing its controllability of dc-link voltages, high efficiency, high linear modulation index, and low common-mode voltage.
- 8 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 73  (1) , 1209-1222
A Quasi-Virtual DPWM Implemented With Split Modulation Waves for DC-Link Voltage Balancing in Four-Level π-Type Inverters
The balance of dc-link voltages is quite a challenge in the four level (4L) π-type inverter, which is the main factor limiting its wide application. In this article, an investigation is conducted to simultaneously balance dc-link voltages and reduce switching losses in 4L π-type inverters. First, the mechanism of the dc-link voltage balancing method based virtual vectors is analyzed, which however will inevitably increase switching losses. To reduce the switching losses, a discontinuous pulse width modulation (DPWM) implemented based on virtual vectors is presented. Then, the vector sequences are rearranged proposing a quasi-virtual DPWM for balancing dc-link voltages of the 4L π-type inverter. And a simplified carrier-based implementation method is introduced with split modulation waves. Auxiliary closed control loops are designed for controlling and balancing dc-link voltages. In addition, the advantage of low common-mode voltage in the quasi-virtual DPWM is analyzed and presented. A three-phase 4L π-type inverter experimental setup is built based on a DSP-FPGA control board. The proposed quasi-virtual DPWM is finally verified by comparative experiments, showing its controllability of dc-link voltages, high efficiency, high linear modulation index, and low common-mode voltage.
- 7 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 40  (8) , 11477-11489
Elliptical-Curve-Based Method for Precise Calculation of Maximum Rotor EMF in DFIG Under Grid Faults
The doubly-fed induction generator (DFIG) is prone to losing control due to high rotor EMF during severe grid faults. Therefore, calculating the maximum rotor EMF of DFIG under different grid faults is the theoretical basis for various low voltage-ride through (LVRT) strategies. In traditional calculation methods, the amplitudes of the positive sequence, negative sequence, and transient dc components of the EMF are summed simply, but each component may not reach its maximum value simultaneously, leading to errors. In this article, the electromagnetic processes of the DFIG are investigated for quantifying the rotor EMF magnitude during grid faults. Then the vector trajectory of the rotor EMF is plotted by using the elliptical curve, and the analytical expression of the rotor EMF is obtained. By finding its extremum point, the maximum value of the rotor EMF under faults is calculated. Through the proposed method, the voltage boundary on the rotor side of DFIG under faults is precisely determined, which can provide reference for DFIG transient analysis and enhanced excitation converter design. At last, the accuracy of the proposed calculation method is experimentally validated through a 1.5-kW DFIG, with errors less than 2% under all fault conditions.
- 7 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 40  (8) , 11477-11489
Elliptical-Curve-Based Method for Precise Calculation of Maximum Rotor EMF in DFIG Under Grid Faults
The doubly-fed induction generator (DFIG) is prone to losing control due to high rotor EMF during severe grid faults. Therefore, calculating the maximum rotor EMF of DFIG under different grid faults is the theoretical basis for various low voltage-ride through (LVRT) strategies. In traditional calculation methods, the amplitudes of the positive sequence, negative sequence, and transient dc components of the EMF are summed simply, but each component may not reach its maximum value simultaneously, leading to errors. In this article, the electromagnetic processes of the DFIG are investigated for quantifying the rotor EMF magnitude during grid faults. Then the vector trajectory of the rotor EMF is plotted by using the elliptical curve, and the analytical expression of the rotor EMF is obtained. By finding its extremum point, the maximum value of the rotor EMF under faults is calculated. Through the proposed method, the voltage boundary on the rotor side of DFIG under faults is precisely determined, which can provide reference for DFIG transient analysis and enhanced excitation converter design. At last, the accuracy of the proposed calculation method is experimentally validated through a 1.5-kW DFIG, with errors less than 2% under all fault conditions.
- 23 December 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 40  (6) , 7628-7633
An Analytical Simplified Algorithm With Unified Zero-Sequence Component Injection for 3L Symmetrical DPWM
Among the existing discontinuous pulsewidth modulation (DPWM) schemes for three-level converters, the symmetrical DPWM can achieve relatively low common-mode voltages, and the redundant vectors are overall distributed equally for balancing the neutral point voltage. However, there is still lack of simple and unified analytical expressions for the zero-sequence component, which can be injected into modulation waves for implementing the symmetrical DPWM. In this letter, to further simplify the implementation of the symmetrical DPWM, a comprehensible derivation process for calculating the zero-sequence component is presented from the perspective of vector synthesis. The dwell times of redundant vectors are intuitively presented and redistributed, and a unified zero-sequence component is analytically derived. Only seven simple equations are required for calculating final modulation waves with the unified zero-sequence component injection, presenting a significantly reduced computation burden.
- 23 December 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 40  (6) , 7628-7633
An Analytical Simplified Algorithm With Unified Zero-Sequence Component Injection for 3L Symmetrical DPWM
Among the existing discontinuous pulsewidth modulation (DPWM) schemes for three-level converters, the symmetrical DPWM can achieve relatively low common-mode voltages, and the redundant vectors are overall distributed equally for balancing the neutral point voltage. However, there is still lack of simple and unified analytical expressions for the zero-sequence component, which can be injected into modulation waves for implementing the symmetrical DPWM. In this letter, to further simplify the implementation of the symmetrical DPWM, a comprehensible derivation process for calculating the zero-sequence component is presented from the perspective of vector synthesis. The dwell times of redundant vectors are intuitively presented and redistributed, and a unified zero-sequence component is analytically derived. Only seven simple equations are required for calculating final modulation waves with the unified zero-sequence component injection, presenting a significantly reduced computation burden.
- 29 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 39  (12) , 15967-15981
An Improved 3L APF Control Strategy Utilizing the Oscillated DC-Link Voltage Command to Enhance the Harmonic-Compensation Performance
Given interactions exist between dc-link voltage oscillations and ac currents in three-level active power filters (3L APF), the output of the outer voltage loop will inevitably affect the current control loop, impairing the harmonic-compensation performance. In this article, the oscillated dc-link voltage command is utilized to enhance the harmonic-compensation performance. First, the dc-link voltage oscillations caused by ac current harmonics in 3L APF converters are mathematically analyzed and derived. Then, to eliminate the dc bias in the integration for calculating the oscillated dc-link voltage command, the multiple second-order generalized integrator frequency-locked loop is adopted and improved by combining with low-pass filters. And an improved 3L APF control strategy utilizing the oscillated dc-link voltage command is proposed to enhance the harmonic-compensation performance. Finally, the proposed 3L APF control strategy is verified by simulations and experiments, presenting an improved harmonic-compensation performance, and a fast dynamic performance of the dc-link voltage can still be guaranteed.
- 29 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 39  (12) , 15967-15981
An Improved 3L APF Control Strategy Utilizing the Oscillated DC-Link Voltage Command to Enhance the Harmonic-Compensation Performance
Given interactions exist between dc-link voltage oscillations and ac currents in three-level active power filters (3L APF), the output of the outer voltage loop will inevitably affect the current control loop, impairing the harmonic-compensation performance. In this article, the oscillated dc-link voltage command is utilized to enhance the harmonic-compensation performance. First, the dc-link voltage oscillations caused by ac current harmonics in 3L APF converters are mathematically analyzed and derived. Then, to eliminate the dc bias in the integration for calculating the oscillated dc-link voltage command, the multiple second-order generalized integrator frequency-locked loop is adopted and improved by combining with low-pass filters. And an improved 3L APF control strategy utilizing the oscillated dc-link voltage command is proposed to enhance the harmonic-compensation performance. Finally, the proposed 3L APF control strategy is verified by simulations and experiments, presenting an improved harmonic-compensation performance, and a fast dynamic performance of the dc-link voltage can still be guaranteed.
- 18 June 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 39  (9) , 11020-11033
A Carrier-Based Discontinuous Space-Vector PWM for Common-Mode Voltage Reduction in Dual-Input Three-Level T-Type Inverters With Unbalanced Neutral-Point Voltages
With unbalanced neutral-point (NP) voltages, the common-mode voltage (CMV) will be increased in dual-input three-level (3L) T-type inverters. Therefore, in this article, a novel discontinuous space-vector pulsewidth modulation for CMV reduction (RCMV-DSVPWM) is proposed. First, the CMV of vectors is analyzed considering unbalanced NP voltages. New space vector diagrams are obtained by abandoning vectors with high CMV, where the nearest three vectors are selected to synthesize the reference vector for reducing output current harmonics. Afterward, subsector divisions and vector sequences are optimized to suppress the CMV and switching losses. Then, to further reduce the computation burden, a cutting-line method is designed for the subsector judgment, and the modulation waves are analytically derived for the carrier-based implementation. Finally, the proposed RCMV-DSVPWM is verified through comparative simulations and experiments under unbalanced NP voltages, where the CMV is effectively suppressed with high efficiencies and low current harmonics.
- 18 June 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 39  (9) , 11020-11033
A Carrier-Based Discontinuous Space-Vector PWM for Common-Mode Voltage Reduction in Dual-Input Three-Level T-Type Inverters With Unbalanced Neutral-Point Voltages
With unbalanced neutral-point (NP) voltages, the common-mode voltage (CMV) will be increased in dual-input three-level (3L) T-type inverters. Therefore, in this article, a novel discontinuous space-vector pulsewidth modulation for CMV reduction (RCMV-DSVPWM) is proposed. First, the CMV of vectors is analyzed considering unbalanced NP voltages. New space vector diagrams are obtained by abandoning vectors with high CMV, where the nearest three vectors are selected to synthesize the reference vector for reducing output current harmonics. Afterward, subsector divisions and vector sequences are optimized to suppress the CMV and switching losses. Then, to further reduce the computation burden, a cutting-line method is designed for the subsector judgment, and the modulation waves are analytically derived for the carrier-based implementation. Finally, the proposed RCMV-DSVPWM is verified through comparative simulations and experiments under unbalanced NP voltages, where the CMV is effectively suppressed with high efficiencies and low current harmonics.