Robert Carl Nikolai Pilawa-Podgurski

Single-stage power factor correction (PFC) ac-dc rectifiers open a pathway to achieve high power density and efficiency in grid-connected rectifiers. A two-stage solution employing a step-up ac-dc stage followed by a step-down dc-dc stage is typically employed to achieve grid to 48 V conversion. This approach suffers from the efficiency penalty of a cascade of power converters and typically lower power density due to the design of two separate power conversion stages. A single-stage, buck-type PFC rectifier where the output dc voltage is lower than the peak ac voltage circumvents these issues. Recently, capacitor-based multi-level power converters have demonstrated superior power density and efficiency compared to conventional two-level designs. This work analyzes and develops a single-stage buck-type PFC rectifier utilizing a six-level flying capacitor multilevel (FCML) converter with active flying capacitor voltage balancing and inductor current control to achieve high performance rectification in a single-stage solution and validates this concept in a hardware prototype. This work is the first to achieve active balancing of the flying capacitor voltages in tandem with PFC operation in a step-down FCML rectifier.

This article presents a high-density, low-profile switching bus converter for vertical power delivery (SBC-VPD) on next-generation high-performance computing platforms. The proposed design is a hybrid switched-capacitor (SC) voltage regulator module (VRM) that directly steps down a 48 V input to the point-of-load (PoL). It leverages the benefits of the switching bus architecture and a high-order SC network with an increased SC stage conversion ratio. Moreover, it improves upon previous SBC iterations through higher-frequency operation, an assistive resonant charge recovery (RCR) circuit enabling near-zero-voltage-switching (ZVS) operation of high-voltage switches, compact packaging with a layout optimized for VPD, custom vertical coupled inductors, and an improved gate drive design. A 48-V-to-PoL hardware prototype was developed and tested up to 600 A to experimentally validate the proposed design and the efficacy of the RCR circuitry. The prototype, with a total height of 4.7 mm, achieves an areal current density of 0.614 A/mm$^{2}$, meeting stringent VPD constraints of $\leq 5$ mm in height and $\geq 0.5$ A/mm$^{2}$ in current density. For 48 V-to-0.65 V conversion, it delivers a power density of 1392 W/in$^{3}$, a peak system efficiency of 85.3%, and a full-load system efficiency of 77.2%. For 48 V-to-0.8 V conversion, it achieves a power density of 1713 W/in$^{3}$, a peak efficiency of 87.1%, and a full-load system efficiency of 79.5%. Additionally, the RCR circuit yields an experimentally verified system efficiency improvement of approximately 1% through switching loss reduction. This prototype advances the state-of-the-art in 48 V-to-PoL conversion, pushing the boundaries of both academic research and commercial products toward higher efficiency and power density.

This work proposes a variable switching frequency scheme for a flying capacitor multilevel (FCML) converter in dc-ac operation to better utilize the output inductor for its rated peak-to-peak current ripple and substantially reduce converter losses over the ac modulation cycle. The proposed technique holds the inductor current ripple constant by leveraging the duty-cycle-dependent inductor current ripple and varies the switching frequency to hold this current ripple constant at its rated design value. Furthermore, this technique can be leveraged to spread conducted electromagnetic interference peaks at both the input and output ports of the inverter. Practical lower switching limits are derived and taken into consideration in developing this approach, and experimental results validate the feasibility in a common microcontroller framework. Hardware results are provided for both 6-level and 8-level FCML inverters and showcase loss reductions and improved electromagnetic interference performance.

This article presents a regulating hybrid switched-capacitor power converter topology suitable for high conversion ratio point-of-load applications where size and weight are important considerations. Coined the dual-inductor switching bus (DISB) converter, the proposed topology merges an initial 2:1 switched capacitor conversion stage with a recently developed symmetric dual-inductor hybrid (SDIH) conversion stage, reaping benefits of both. The initial 2:1 voltage reduction stage significantly reduces the overall volume/weight of flying capacitors, while the SDIH stage offers reduced component count and an excellent switch stress figure of merit. A preliminary 50 W hardware prototype validates this topology while employing derated gallium nitride (GaN) switches to enable operation in harsh environments, such as aerospace. Further leveraging topology-specific properties, we also describe the implementation of two highly complimentary circuit blocks; a high density gate drive solution and a technique termed resonant charge recovery (RCR), which serves to reduce overall converter losses by up to 37% while occupying < 1% of total converter volume. The resulting prototype achieves a very high measured power density of 2020 W/in$^{3}$ (123.3 kW/L) with 87.3% full-load conversion efficiency (90.1% peak efficiency), while switching at 1 MHz and performing direct 48-V-to-1 V conversion.

Drivetrain efficiency and weight represent significant barriers toward the development of future electric aircraft. Multilevel inverter designs have achieved impressive performance in these applications, with the flying capacitor multilevel (FCML) topology demonstrating particular promise. FCML converters contain many active devices along with associated gate drive circuitry. In order to achieve simultaneous goals of high density, high efficiency, and good signal integrity, the printed-circuit-board (PCB) layout and physical design of the converter is of utmost importance. In this work, a stacked PCB design is presented, which shields the low-voltage gate signals from interference, while also enabling an uninterrupted power path, low commutation loop inductance, and compact volume. A 400 V, 6.25 kW, 8-level FCML prototype is fabricated, which achieves 89 kW/kg specific power, 214 kW/L power density and 98.64$\%$ peak efficiency, with a THD of 0.72$\%$.

This article presents methods for modeling capacitor voltage dynamics in the Flying Capacitor Multilevel (FCML) converter and closed-loop control techniques for regulating the capacitor voltages to their nominal balanced values. A small-signal plant model is derived by studying the open-loop capacitor voltage dynamics using a linear-ripple model of the inductor current. Perturbations to the switching signals acting as control inputs are defined, and their impacts on the average currents flowing into the flying capacitors are identified. Unlike prior works based on averaging, the proposed plant models accurately capture the impact of the inductor current ripple on the average capacitor currents and yield valid models of capacitor voltage dynamics at light-load conditions. Using the proposed control inputs, the small-signal system is shown to be completely controllable, and a state-feedback controller is presented to damp the natural capacitor voltage oscillation. Plant models and controller structures are presented for all three operating modes of the four-level FCML converter. Experimental measurements of a hardware prototype verify the presented open- and closed-loop models. The capacitor voltage responses to supply voltage step-transients significantly improve with the proposed active balancing controller across the full load range.

This work presents a generalized averaged (dynamic phasor) model for capacitor voltage dynamics in the flying capacitor multilevel converter. The “natural balancing” dynamics of capacitor voltages under symmetric phase-shifted pulsewidth modulation are derived and verified against time-domain simulations. The model is simplified to a reduced-order form using singular perturbation theory, and modal analysis techniques are developed to identify the minimum model complexity for a given design and operating point. A small-signal equivalent of the reduced-order model is subsequently developed to characterize known light-load instabilities in systems using closed-loop “active balancing” control. Results obtained from the model for natural and active balancing scenarios are compared to experimental characterization of a hardware prototype.