Hervé Morel
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Hervé Morel has a total of 101 co-authors. Here are the top co-authors by number of shared publications:
- Dominique Planson
Université Claude Bernard Lyon 1
9 shared publications - Cyril Buttay
Université de Lyon, CNRS
7 shared publications - Camille Sonneville
Univ Lyon, INSA Lyon, Univ. Claude Bernard Lyon 1
3 shared publications - Christophe Raynaud
University of Lyon
3 shared publications - Hatem Garrab
Laboratoire dlectronique et de Micro-lectronique, University of Monastir, Monastir, Tunisia
3 shared publications - Luong Viet Phung
Université Claude Bernard Lyon 1
3 shared publications
Latest Publications
- Open Access
- 1 June 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 90078-90085
Electro-Optical Voltage Probe on the Pockels Effect: Experimental Validation Up to 4-kV
This paper presents a high-voltage measurement probe based on the Pockels effect. The sensor provides galvanic isolation for electric field sensing, featuring an intrinsic bandwidth of 1 GHz. A key advantage is its inherent immunity to electromagnetic interference (EMI), which combined with galvanic isolation enables clean measurements in high-noise environments typical of wide-bandgap (WBG) device characterization. The probe integrates a planar capacitor-based electric-field-to-voltage transformer connected to the drain (D) and source sense (SS) contacts. This transformer is combined with a Pockels-effect sensor, enabling differential measurement of VDS without direct electrical contact, thereby avoiding voltage limitations and bandwidth degradation. The probe performance is experimentally validated under transients up to 4 kV during silicon carbide (SiC) MOSFET avalanche under unclamped inductive switching (UIS) conditions. Results show excellent agreement with a passive reference probe and demonstrate a linear response from 0 V to 4 kV, validating the probe capability for accurate, high-speed, and high-voltage monitoring in power electronics applications.
- 1 June 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 90078-90085
Open AccessElectro-Optical Voltage Probe on the Pockels Effect: Experimental Validation Up to 4-kV
This paper presents a high-voltage measurement probe based on the Pockels effect. The sensor provides galvanic isolation for electric field sensing, featuring an intrinsic bandwidth of 1 GHz. A key advantage is its inherent immunity to electromagnetic interference (EMI), which combined with galvanic isolation enables clean measurements in high-noise environments typical of wide-bandgap (WBG) device characterization. The probe integrates a planar capacitor-based electric-field-to-voltage transformer connected to the drain (D) and source sense (SS) contacts. This transformer is combined with a Pockels-effect sensor, enabling differential measurement of VDS without direct electrical contact, thereby avoiding voltage limitations and bandwidth degradation. The probe performance is experimentally validated under transients up to 4 kV during silicon carbide (SiC) MOSFET avalanche under unclamped inductive switching (UIS) conditions. Results show excellent agreement with a passive reference probe and demonstrate a linear response from 0 V to 4 kV, validating the probe capability for accurate, high-speed, and high-voltage monitoring in power electronics applications.
- Open Access
- 10 September 2025
- Published by Trans Tech Publications, Ltd. in Key Engineering Materials
- Vol. 1023, 1-6
Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes
This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.
- 10 September 2025
- Published by Trans Tech Publications, Ltd. in Key Engineering Materials
- Vol. 1023, 1-6
Open AccessMatching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes
This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.
- Open Access
- 5 September 2025
- Published by Trans Tech Publications, Ltd. in Key Engineering Materials
- Vol. 1021, 1-6
Electrical Characterization of HV (10 Kv) Power 4H-SiC Bipolar Junction Transistor
In this paper, the static and dynamic characterization of a High Voltage (10kV) 4H-SiC Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm-2. The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV. The study concludes that 4H-SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.
- 5 September 2025
- Published by Trans Tech Publications, Ltd. in Key Engineering Materials
- Vol. 1021, 1-6
Open AccessElectrical Characterization of HV (10 Kv) Power 4H-SiC Bipolar Junction Transistor
In this paper, the static and dynamic characterization of a High Voltage (10kV) 4H-SiC Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm-2. The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV. The study concludes that 4H-SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.
- Open Access
Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs
The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan.Open AccessTest Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs
The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan. - 5 June 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 71 (5) , 5285-5295
Physics-Based Strategies for Fast TDDB Testing and Lifetime Estimation in SiC Power MOSFETs
To expedite testing, time-dependent dielectric breakdown (TDDB) analyses are conducted on commercial 4H-SiC mosfet s at high gate-to-source voltages ( $\bm {V_{GS}}$ ), under Fowler–Nordheim conduction only. However, as inferred, such conditions induce impact ionization-generated holes in the dielectric layer (SiO $\bm {_{2}}$ ), resulting in a state transition in the effective dipolar moment. This accelerates the SiO $\bm {_{2}}$ degradation leading to an overestimation of its intrinsic lifetime at typical $V_{GS}$ values for gate driving in power converters. To address this, a physics-based approach is proposed to design TDDB tests under such conditions and to correct the intrinsic lifetime prediction at nominal $\bm {V_{GS}}$ values, shortening the testing time by up to two orders of magnitude. Thus, the proposed method is a well-suited candidate to be considered in SiC power device qualification standards, still under development.
- 5 June 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 71 (5) , 5285-5295
Physics-Based Strategies for Fast TDDB Testing and Lifetime Estimation in SiC Power MOSFETs
To expedite testing, time-dependent dielectric breakdown (TDDB) analyses are conducted on commercial 4H-SiC mosfet s at high gate-to-source voltages ( $\bm {V_{GS}}$ ), under Fowler–Nordheim conduction only. However, as inferred, such conditions induce impact ionization-generated holes in the dielectric layer (SiO $\bm {_{2}}$ ), resulting in a state transition in the effective dipolar moment. This accelerates the SiO $\bm {_{2}}$ degradation leading to an overestimation of its intrinsic lifetime at typical $V_{GS}$ values for gate driving in power converters. To address this, a physics-based approach is proposed to design TDDB tests under such conditions and to correct the intrinsic lifetime prediction at nominal $\bm {V_{GS}}$ values, shortening the testing time by up to two orders of magnitude. Thus, the proposed method is a well-suited candidate to be considered in SiC power device qualification standards, still under development.
- Open Access
- 3 June 2023
- Published by MDPI AG in Electronics
- Vol. 12 (11) , 2529
Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs
The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the measurement, even for measurements following degrading voltage bias stress on both drain and gate.- 3 June 2023
- Published by MDPI AG in Electronics
- Vol. 12 (11) , 2529
Open AccessThreshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs
The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the measurement, even for measurements following degrading voltage bias stress on both drain and gate. - 26 January 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Control Systems Technology
- Vol. 31 (4) , 1636-1648
Robust Regulation of a Power Flow Controller via Nonlinear Integral Action
This article considers a robust output set-point tracking problem for an $m$ -terminal power flow controller (PFC) for meshed dc micro-grids. The PFC is a power electronics device used to control the power flow at a node in the meshed grid and may act as a dc circuit breaker. The system is modeled by state-space bilinear dynamics coupled with a polynomial output. In the proposed design, the plant is first extended with an integral action processing the regulation error. The cascaded model composed of the plant and the integrator is then stabilized using a saturated state-feedback law, designed with a forwarding approach. An anti-windup function is added to cope with transient saturations. A tuning method is proposed to set the controller gains along the available degrees of freedom with respect to a cost function. The stability of the closed loop is guaranteed for any compact set of initial conditions and for small parametric variations around the nominal set point. Experiments have been carried out and these properties are successfully assessed on a tenth-scale experimental setup.
- 26 January 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Control Systems Technology
- Vol. 31 (4) , 1636-1648
Robust Regulation of a Power Flow Controller via Nonlinear Integral Action
This article considers a robust output set-point tracking problem for an $m$ -terminal power flow controller (PFC) for meshed dc micro-grids. The PFC is a power electronics device used to control the power flow at a node in the meshed grid and may act as a dc circuit breaker. The system is modeled by state-space bilinear dynamics coupled with a polynomial output. In the proposed design, the plant is first extended with an integral action processing the regulation error. The cascaded model composed of the plant and the integrator is then stabilized using a saturated state-feedback law, designed with a forwarding approach. An anti-windup function is added to cope with transient saturations. A tuning method is proposed to set the controller gains along the available degrees of freedom with respect to a cost function. The stability of the closed loop is guaranteed for any compact set of initial conditions and for small parametric variations around the nominal set point. Experiments have been carried out and these properties are successfully assessed on a tenth-scale experimental setup.
- Open Access
Deep Level Transient Fourier Spectroscopy Investigation of Electron Traps on AlGaN/GaN-on-Si Power Diodes
Many kinds of defects are present in AlGaN/GaN-on-Si based power electronics devices. Their identification is the first step to understand and improve device performance. Electron traps are investigated in AlGaN/GaN-on-Si power diodes using deep level transient Fourier spectroscopy (DLTFS) at different bias conditions for two Schottky contact’s etching recipes. This study reveals seven different traps corresponding to point defects. Their energy level ET ranged from 0.4 eV to 0.57 eV below the conduction band. Among them, two new traps are reported and are etching-related: D3 (ET = 0.47–0.48 eV; σ ≈ 10−15 cm2) and D7 (ET = 0.57 eV; σ = 4.45 × 10−12 cm2). The possible origin of the other traps are discussed with respect to the GaN literature. They are proposed to be related to carbon and nitrogen vacancies or to carbon, such as CN-CGa. Some others are likely due to crystal surface recombination, native defects or a related complex, or to the nitrogen antisite: NGa.
Open AccessDeep Level Transient Fourier Spectroscopy Investigation of Electron Traps on AlGaN/GaN-on-Si Power Diodes
Many kinds of defects are present in AlGaN/GaN-on-Si based power electronics devices. Their identification is the first step to understand and improve device performance. Electron traps are investigated in AlGaN/GaN-on-Si power diodes using deep level transient Fourier spectroscopy (DLTFS) at different bias conditions for two Schottky contact’s etching recipes. This study reveals seven different traps corresponding to point defects. Their energy level ET ranged from 0.4 eV to 0.57 eV below the conduction band. Among them, two new traps are reported and are etching-related: D3 (ET = 0.47–0.48 eV; σ ≈ 10−15 cm2) and D7 (ET = 0.57 eV; σ = 4.45 × 10−12 cm2). The possible origin of the other traps are discussed with respect to the GaN literature. They are proposed to be related to carbon and nitrogen vacancies or to carbon, such as CN-CGa. Some others are likely due to crystal surface recombination, native defects or a related complex, or to the nitrogen antisite: NGa.
- Open Access
Capacitance Temperature Dependence Analysis of GaN-on-Si Power Transistors
Many kinds of defects are present in the different layers of GaN-on-Si epitaxy. Their study is very important, especially because they play a significant role on the device characteristics. This paper investigates the cause of the temperature dependence of the output and Miller capacitance at three temperatures: 25 °C, 75 °C and 150 °C of GaN-on-Si power transistors. In particular, this study focuses on the temperature dependence of the depletion voltage seen in these characteristics due to the progressive depletion of the two-dimensional electron gas (2DEG) under the device field plates. First, variations of the epitaxial growth are studied, showing that the intrinsic carbon concentration does not play a significant role. Secondly, the deep acceptor trap origin of the temperature dependence is analyzed with a TCAD simulation study. Thirdly, by adjusting TCAD parameters and binding them with experimental concentrations to fit experimental data, trap properties were obtained. The comparison of these properties with the acceptor traps in the literature suggests that the origin is a gallium vacancy tied to oxygen atom(s) on the N site.
Open AccessCapacitance Temperature Dependence Analysis of GaN-on-Si Power Transistors
Many kinds of defects are present in the different layers of GaN-on-Si epitaxy. Their study is very important, especially because they play a significant role on the device characteristics. This paper investigates the cause of the temperature dependence of the output and Miller capacitance at three temperatures: 25 °C, 75 °C and 150 °C of GaN-on-Si power transistors. In particular, this study focuses on the temperature dependence of the depletion voltage seen in these characteristics due to the progressive depletion of the two-dimensional electron gas (2DEG) under the device field plates. First, variations of the epitaxial growth are studied, showing that the intrinsic carbon concentration does not play a significant role. Secondly, the deep acceptor trap origin of the temperature dependence is analyzed with a TCAD simulation study. Thirdly, by adjusting TCAD parameters and binding them with experimental concentrations to fit experimental data, trap properties were obtained. The comparison of these properties with the acceptor traps in the literature suggests that the origin is a gallium vacancy tied to oxygen atom(s) on the N site.