Ming Liu

Wurtzite Al _1-x Sc _x N ferroelectrics exhibit exceptional polarization and thermal stability, making them highly promising for a wide range of electronic applications. However, a more profound understanding is required regarding the atomic-scale mechanism through which cation substitution lowers the switching energy barrier and thus reduces the coercive field. We used spherical aberration–corrected transmission electron microscopy to reveal a periodic modulation of cation-anion spacing along the polarization direction, forming alternating atomic dipole layers. This modulation arises from energetically favorable chemical ordering of aluminum and scandium atoms between adjacent layers, with layer-resolved asymmetry in atomic arrangement. In situ imaging directly captures atomic-scale, noncollective, stepwise polarization switching, revealing intermediate states and local spacing fluctuations. Compositional inhomogeneity in these dipole layers creates multiple transient states that reduce the switching energy barrier. Our findings connect atomic-scale dipole structures to polarization switching kinetics, enabling the rational design of wurtzite ferroelectrics.

Computing-in-memory (CIM) is a promising paradigm for energy- and area-efficient implementation of the heavy general matrix multiplication (GEMM) operations, especially in the evolving deep learning algorithms. Though existing CIM macros have demonstrated remarkable energy/area efficiency, the corresponding metrics of the system-level CIM chips degrade due to the peripheral components, including external SRAM and accumulation circuits. First, the separated design of CIM macros and peripheral components leads to suboptimal solutions, suffering high input/output SRAM access power, loose layout with long data paths, bulk clock trees, and so on. Second, the input/output SRAM takes a majority area proportion, which is inevitable in existing system-level CIM chips. Besides, continuous power/area optimization on the CIM macro itself also contributes to the system-level energy/area efficiency. Third, the accumulation module after the CIM macro leads to redundant power consumption due to the unnecessary high-bit-position computation. This work presents a system-in-one-macro CIM chip, integrating all system-level components (except the control logic) into one single macro, indicating a significant difference in the design flow with three detailed innovations: 1) to replace the power/area consuming external SRAMs, a high-density leakage-eliminated 2T1C embedded DRAM (eDRAM) is designed for input activation and output result storage; 2) a capacitor (cap)-over-logic one-transistor-one-capacitor (1T1C) eDRAM array with shared-preprocessing MUX-based CIM circuits is proposed to further improve the macro-level CIM energy/area efficiency and density; and 3) utilizing the low-activity property of the high-bit-position accumulation, a low-MAC-aware near-memory-computing (NMC) circuit is designed to reduce the redundant accumulation power. The 28-nm fabricated system-in-one-macro CIM chip demonstrates 51.6 TOPS/W energy efficiency, 1.53 TOPS/mm² area efficiency, and 2.22-Mb/mm² storage density.

Traditional Dynamic Random Access Memory (DRAM) technology faces significant scaling challenges as device dimensions approach fundamental physical constraints. Indium-gallium-zinc-oxide (IGZO) has emerged as a potential solution to these scaling limitations, offering advantageous characteristics such as ultra-low leakage currents and compatibility with low-temperature fabrication processes. This paper reviews recent advancements in Two-Transistor Zero-Capacitor (2T0C) DRAM technology that utilize IGZO materials, with a focus on innovations in device architecture and system-level integration.

While the internet of things (IoT) enhances global connectivity through trillions of sensors, the sensory signals are weak and require precise amplification and rapid transmission via thin-film transistor (TFT) interfaces, which must uphold high voltage gain and wide operating frequency range. In this work, we demonstrate a source-gated transistor (SGT) architecture integrating chemical vapor deposition (CVD)-grown monolayer MoS₂ with thin high-k dielectrics. This transistor achieves subthreshold operation with high intrinsic gain and wide operating frequency range, even at an 80 nm channel-length (L_CH). The optimization of output resistance, transconductance and subthreshold swing yields an SGT intrinsic gain exceeding 2.4×10³, with no degradation as L_CH scales from 1000 nm down to 80 nm. Additionally, benefitting from the ultra-short 80 nm L_CH, microwave measurements show a high cut-off frequency of 208 MHz in the subthreshold regime. A monolithically integrated common-source amplifier operating in the subthreshold regime exhibits a high gain of 249 V/V at low supply voltage (0.5 V) and ultra-low power ( ~ 0.17 nW), indicating a promising path toward a universal high-performance transistor solution for high gain, high frequency, and ultra-low power applications.

An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing the contact metallization and its interface through an in-situ ozone oxidation method, the vertical dual-gate transistor exhibits a high on-state current and small subthreshold slope as well as high thermal stability and device variation. Furthermore, a four-bit multi-bit operation is demonstrated with an ultra-scaled 4F² two-transistors-zero-capacitor dynamic random-access memory to further increase the storage density. The approach presented here provides a promising alternative to high-density three-dimensional dynamic random-access memory integration as a means for more efficient near memory computing for artificial intelligence systems.

Computing-in-memory (CIM) chips have demonstrated promising energy efficiency for artificial intelligence (AI) applications such as neural networks (NNs), Transformer, and recommendation system (RecSys). However, several challenges still exist. First, a large gap between the macro and system-level CIM energy efficiency is observed. Second, several memory-dominate operations, such as embedding in RecSys and non-linear functions in NN/Transformer, require heavy off-chip access. To solve these challenges, this work presents an energy-efficient CIM-CAM processor for both NN and RecSys applications with three main innovations. First, we propose a reconfigurable Zig-Zag memory access structure, enabling flexible adjacent connections between SRAMs and CIM arrays to minimize SRAM access power. Second, a backbone-systolic (BKS) CIM array is implemented to avoid a long accumulation path with better data reuse between CIM macros. Third, a distribution-aware block-/self-gating (DABG) content-addressable-memory (CAM) is proposed to reduce off-chip access and on-chip search power for the memory-dominate embedding operations in RecSys. The fabricated 28-nm CIM-CAM chip achieves 37.9–81.5 TOPS/W for NN and 12.3–56.1 nJ/request for RecSys and highlights the improvement of system-to-macro efficiency ratio (SMER) by 9.2% over the trendline of the state-of-the-art system-level CIM processors.

Edge artificial intelligence systems require higher frequency due to intensive computational demands, while most traditional entropy sources decay with frequency. This work shows the physical properties of the Fe-diode devices are ideal for edge systems with high frequencies and dramatic temperature changes. The noise density of Fe-diode can be modified by the amplitude of the read voltage and remains stable at high frequencies and temperature fluctuations. A Bayesian neural network with Fe-diode devices is experimentally implemented in high-speed, high-density silicon-based chips. This hierarchical Bayesian neural network is demonstrated on 3D 16-layer Fe-diode array based on unified entropy source and 4-state synapse. Properties including high area efficiency, wide working temperature range, low energy in-situ training, high recognition accuracy are finally achieved.

Digital twins, which replicate real-world entities through computational models, are transforming manufacturing and automation. While recent advances in machine learning have enabled data-driven digital twin development using discrete-time data and finite-depth models on digital hardware, these approaches face significant limitations. They struggle to capture continuous-time dynamics and model complex systems, and suffer from substantial time and energy overheads due to physically separated storage and processing as well as frequent analog-digital (A/D) conversions. Here, we propose a memristive neural ordinary differential equation (ODE) solver for digital twins. Our approach is intrinsically time-continuous using infinite-depth neural networks to model complex dynamics. Fully analog memristor arrays collocate storage and computation, addressing the von Neumann bottleneck and reducing A/D conversion requirements. We experimentally validate our solver on digital twins of HP variable-resistor model and Lorenz96 dynamics, demonstrating a 166.5-fold/369.3-fold speedup and a 499.0-fold/673.9-fold improvement in energy efficiency, respectively. This work paves the way to future digital twins for Industry 4.0.

In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable DVSN boosting, with a record-high ratio (VSN/ VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and DVSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array