Joonki Suh

Two‐dimensional (2D) memristors are promising for low‐power and high‐speed neuromorphic hardware. However, their performance under circuit‐level constraints remains limited because resistive switching relies on native defects, hindering precise control of filament formation. Here, we report 2D MoTe ₂ memristors that integrate deterministic switching‐path density engineering with CMOS‐compatible one‐transistor‐one‐memristor (1T‐1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (α _p /α _d = 0.019/0.2), enabled by a balanced interplay between filament formation and confinement. Furthermore, monolithic integration with silicon transistors enables gate‐tunable compliance control, which suppresses variability and stabilizes array‐level operation. The resulting 1T‐1 M arrays exhibit a wide dynamic range (∼22×), and minimal potentiation/depression variation (7.95%/6.22%). Device‐aware simulations based on multilayer perception, convolutional neural network, and autoencoder models confirm improved learning accuracy compared to passive arrays. This work establishes a materials‐to‐circuit design framework that links defect‐path engineering with transistor‐assisted current control, providing a practical pathway toward 2D neuromorphic hardware.

Two‐dimensional (2D) semiconductors are poised to extend logic technology to the atomic‐thickness limit, yet monolayer complementary metal‐oxide‐semiconductor (CMOS) has been largely hampered by polarity‐dependent, thermionic‐emission‐dominated contacts that preclude a unified injection solution. Here, we introduce degenerately doped, crystalline SnSe ₂ as a universal source‐side van der Waals (vdW) injector capable of enforcing all‐tunneling carrier injection into both p ‐ and n ‐type monolayer channels. The combination of a large electron affinity (∼5.1 eV), degenerate carrier density (>10 ¹⁹ cm ⁻³ ), and atomically uniform vdW interfacial coupling enables polarity‐tailored tunneling mechanisms while effectively suppressing interfacial gap states. In p ‐type WSe ₂ , a type‐III (broken gap) alignment drives efficient band‐to‐band tunneling, yielding a >1000‐fold enhancement in drive current over conventional metal electrodes. In n ‐type MoS ₂ , the SnSe ₂ injector forms a type‐I heterojunction within the sub‐depletion‐width monolayer body, enabling a gate‐tunable injection that evolves from field‐controlled Fowler–Nordheim‐like tunneling to thickness‐limited tunneling, achieving an on/off ratio > 10 ⁹ and a subthreshold swing below 70 mV dec ⁻¹ . Integrating this single‐material injector, we demonstrate a monolayer CMOS inverter with a maximum voltage gain of ∼340 at V _DD = 2 V, establishing degenerate SnSe ₂ as a dual‐polarity vdW injector and providing a platform for high‐performance, low‐power 2D integrated circuits.

Achieving the theoretical performance of 2D molybdenum disulfide (MoS ₂ ) electronics is currently bottlenecked by interfacial contamination derived from lithographic processing. A critical, yet often overlooked, mechanism is the interaction between photoresist (PR) and plasma, which chemically alters the interface. In this work, we elucidate the atomistic origin of this degradation: theoretical calculations based on molecular dynamics (MD) and density functional theory (DFT) reveal that plasma exposure functionalizes the PR with oxygen, drastically increasing its adsorption energy on the MoS ₂ surface from −1.15 to −2.36 eV. This doubling of adsorption energy creates thermodynamically stable, hardened residues that resist conventional removal methods. To overcome this fundamental limitation, we introduce a universal prevention‐first strategy: Sacrificial Metal Mask Lithography. By utilizing a sacrificial layer to physically isolate the channel, we shield the MoS ₂ from reactive plasma species, preventing the formation of hardened residue entirely. This strategy results in a ten‐fold reduction in contact resistance ( R _C ) from 2.59 × 10 ⁶ Ω·µm to 2.58 × 10 ⁵ Ω·µm and an order‐of‐magnitude enhancement in on‐current. Crucially, we demonstrate the universality of this method by successfully applying it to top‐gated transistor arrays, electron‐beam lithography (EBL), and atomic layer deposition (ALD)‐synthesized films.

Two-dimensional (2D) transition-metal dichalcogenides are attractive for nanoelectronics and energy harvesting, where thermal transport critically impacts device reliability, performance, and energy efficiency. Here, we establish hierarchical defect engineering in monolayer MoS2 by combining growth-programmed mesoscale grain boundaries with He+-irradiation-induced atomic vacancies and quantify how these multiscale defects govern the in-plane thermal conductivity (κ) and its temperature dependence. By integrating opto-thermal Raman thermometry and variance-reduced Monte Carlo simulations, we decouple the distinct, temperature-dependent roles of these multiscale defects in phonon scattering. We reveal that while grain boundaries impose an approximately temperature-insensitive suppression by limiting long-mean-free-path phonons, vacancies specifically target high-frequency phonons, thereby dominating scattering at elevated temperatures. This complementary behavior enables a synergetic 85% suppression of κ at an ambient temperature (Ta) of 50 K, from 42.24 to 6.25 W m–1 K–1, confirming broadband phonon blocking. At Ta = 300 K, vacancy-induced scattering overrides grain boundary effects, causing the κ of highly defective single- and polycrystalline samples to converge. Our work provides fundamental design rules for tuning phonon transport in 2D materials and for deploying them in thermal management and thermoelectric applications.

Selector-only memory (SOM) integrates signal selection and data storage within a single chalcogenide element through polarity-dependent threshold voltage (Vth) modulation, offering a compact route to high-density nonvolatile storage. However, its practical multilevel deployment has been hindered by three barriers: the toxicity of arsenic-containing glasses, stochastic Vth programming, and state-destructive readout. Here, we demonstrate deterministic multibit programming combined with a nondestructive spike-frequency readout in an arsenic-free Ge–Se–Te SOM. Rational blending of Se and Te anions stabilizes the amorphous network, affording a wide memory window (∼2.0 V) for multistate margins, together with low variability (5–6%), extended endurance (>106 cycles), and thermal stability up to 400 °C. Transient analysis of post-threshold voltage redistribution reveals that Vth placement is governed jointly by the internal electric field and programming current, rather than total power dissipation. Guided by this insight, we achieve reproducible 2-bit operation with ∼0.5 V interstate separation sustained over 500 cycles in both individual devices and a 128-cell array. Under subthreshold bias, capacitive charging produces current spikes whose frequency encodes the stored state (0.5–2.5 MHz), enabling robust readout with minimal Vth disturbance. These results establish nontoxic chalcogenide glasses with decoupled write and read protocols as a scalable design framework for reliable multibit SOM storage.

Van der Waals (vdW) epitaxy can integrate lattice-mismatched crystals with atomically sharp, pristine interfaces. However, translating this concept to atomic layer deposition (ALD), a standard for low-temperature, layer-by-layer growth, remains challenging because precursors adsorb transiently on chemically inert vdW basal planes, leading to physisorption-limited nucleation and poor crystalline ordering. Here, we introduce diffusion-steered epitaxial ALD (Epi-ALD), redefining vdW surfaces as programmable kinetic-thermodynamic landscapes and demonstrate highly crystalline tellurium at 150°C. Epi-ALD couples surface-potential-encoded physisorption with long-range diffusion to promote ordered nucleation and epitaxial alignment. This “soft” pathway enables strain-free tellurium epitaxy with a pristine vdW gap (∼1.4 angstrom) despite lattice mismatch (>3.6%) and generalizes across multiple vdW templates. Retaining hallmark advantages of ALD including scalability and uniformity, we further program in-plane orientation through vdW symmetry engineering to achieve quasi-single-crystalline tellurium films with pronounced anisotropy and a chiral anomaly signature. Our work establishes a universal, low-thermal-budget approach for integrating vdW materials and expands the scope of epitaxy within the ALD paradigm.

Perovskite/Si tandem (PST) cells have recently achieved record‐breaking efficiencies, positioning them as a leading technology in next‐generation photovoltaics. However, maintaining long‐term operational stability and ensuring consistent performance under realistic fabrication and deployment conditions remain critical challenges. To overcome these issues, we propose a dual optimization strategy that integrates electrical interface engineering with tailored optical design. First, we introduce a novel self‐assembled monolayer containing a propoxyphenyl‐based linker, which enhances molecular packing density and significantly increases the shunt resistance of the device. This interface modification improves hole selectivity and broadens fabrication tolerance by increasing the allowable range of current mismatch between sub‐cells while maintaining high efficiency. Second, we design a light‐scattering film by embedding shape‐controlled phosphor particles into a textured poly(dimethylsiloxane) (PDMS) matrix, which improves light harvesting through UV down‐conversion and diffuse transmission. As a result, we achieve a PCE of 31.66% for a 1 cm ² device. These findings demonstrate a synergistic design approach and offer a practical route toward robust, high‐efficiency PST devices with improved fabrication tolerance.

Ion‐gated transistors inherently exhibit time‐dependent behavior governed by ionic motion associated with electric double‐layer formation; however, their practical implementation has been limited by insufficient control over ionic dynamics and poor compatibility with scalable thin‐film integration. Here, we present carbon nanotube (CNT) solid‐ion‐gated transistors (sIGTs) that allow the wide‐range engineering of ionic dynamics while remaining fully compatible with wafer‐scale thin‐film processing. Tunable ionic conductance is achieved by ionic content engineering in the film and thickness scaling into the sub‐micron regime, enabling ionic time constants from microseconds to milliseconds. CNT sIGTs demonstrate robust DC operation at low ionic content with an optimized polymer matrix and wafer‐scale fabrication on flexible substrates. Frequency‐dependent gate modulation governed by ionic conductance is systematically investigated through electrical impedance spectroscopy and small‐signal analysis, including a comparison of the −3 dB cutoff frequency and the transit frequency. This analysis provides direct insight into the relationship between ionic conductance and frequency‐dependent device response, exhibiting consistent trends across both two‐terminal and three‐terminal device configurations. Monolithic three‐dimensional integration of two‐tier CNT sIGTs with engineered dynamic responses is demonstrated as a compact dual‐timescale physical reservoir for neuromorphic computing that enables classification of time‐varying inputs using a single readout layer.

Non‐centrosymmetric stacking in boron nitride (BN) enables out‐of‐plane polarization, offering a route toward 2D dielectrics with embedded nonvolatile functionality. However, achieving uniform, wafer‐scale growth of metastable Bernal‐stacked BN (bBN) remains challenging, as it requires breaking interlayer inversion symmetry. Here, we demonstrate the wafer‐scale epitaxial growth of single‐crystal bBN bilayers on Ni(111)/sapphire substrates using metal‐organic chemical vapor deposition. By employing a flow‐modulation epitaxy approach, we enhanced surface reaction kinetics while suppressing secondary nucleation, thereby enabling self‐limiting growth of uniform bilayer bBN films. Monoatomic Ni step edges deterministically enforced the AB stacking order, energetically stabilizing the bilayer configuration by lifting the degeneracy of competing stacking orientations, as confirmed by atomic‐resolution imaging and density functional theory calculations. The resulting bBN films served as atomically thin dielectric interlayers in top‐gated molybdenum disulfide (MoS ₂ ) transistor arrays, yielding spatially uniform device performance across the wafer and enabling nonvolatile ferroelectric switching of the MoS ₂ channels via polarization reversal in the bBN interlayer. These results expand the understanding of step‐edge‐guided growth mechanisms for controlling stacking order and layer number in metastable 2D materials, and demonstrate a reliable wafer‐scale approach to phase‐controlled synthesis of single‐crystal bBN bilayers with their integration as functional 2D dielectrics for practical electronic applications.