Alireza Karimi-Bidhendi
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Alireza Karimi-Bidhendi has a total of 28 co-authors. Here are the top co-authors by number of shared publications:
Payam Heydari
Dept. of Electrical Engineering and Computer Science, UCI, Irvine, CA, 92697, USA
10 shared publications- Zoran Nenadic
University of California, Irvine
9 shared publications An H. Do
Department of Neurology, University of California at Irvine, Irvine, CA, USA
8 shared publicationsCharles Y. Liu
Rancho Los Amigos National Rehabilitation Center, Downey, CA, USA
6 shared publicationsPo T. Wang
Dept. of Biomedical Engineering, University of California Irvine (UCI), Irvine, CA, 92697, USA
6 shared publicationsColin M. McCrimmon
Department of Biomedical Engineering, University of California, Irvine, CA, USA
5 shared publications
Latest Publications
- 3 March 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 67 (12) , 2868-2872
A Study of Multi-Phase Injection on Accelerating Crystal Oscillator Start-Up
As a widely used reference signal generator in communication systems, a crystal oscillator (XO) exhibits an unduly long start-up time TS. External signal injection is an effective method to kick-start the XOs. However, the deviation from ideal injection frequency, which easily occurs and is hardly controllable, limits its effectiveness. This work analyzes the XO start-up behavior when differentially excited by an external oscillator and introduces a multi-phase signal injection method to mitigate the shortcomings of conventional injection techniques. Simulation results of an XO designed in a 180 nm CMOS process show that the proposed technique is capable of lowering TS close to minimum theoretical limit.
- 3 March 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 67 (12) , 2868-2872
A Study of Multi-Phase Injection on Accelerating Crystal Oscillator Start-Up
As a widely used reference signal generator in communication systems, a crystal oscillator (XO) exhibits an unduly long start-up time TS. External signal injection is an effective method to kick-start the XOs. However, the deviation from ideal injection frequency, which easily occurs and is hardly controllable, limits its effectiveness. This work analyzes the XO start-up behavior when differentially excited by an external oscillator and introduces a multi-phase signal injection method to mitigate the shortcomings of conventional injection techniques. Simulation results of an XO designed in a 180 nm CMOS process show that the proposed technique is capable of lowering TS close to minimum theoretical limit.
- 26 June 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 54 (9) , 2543-2554
Study and Design of a Fast Start-Up Crystal Oscillator Using Precise Dithered Injection and Active Inductance
This paper presents a theoretical study and design of two techniques used to reduce start-up time (T S ) and energy (E S ) of Pierce crystal oscillator (XO). An analytical study of precise injection on a crystal resonator is introduced, and based on this paper, a relaxation oscillator with a dithered frequency is designed. Next, a study of negative resistance of XO's active circuitry and a method to boost its value beyond the limit set by a crystal static capacitor are presented. A gyrator-C active inductor with high linearity is developed to accelerate the start-up process by boosting the negative resistance. A prototype integrating these techniques is fabricated in a 180-nm CMOS process and shows a significant improvement compared with the prior art. Specifically, TS and ES are reduced by 102.7× and 2.9×, compared with the XO start-up with no assisting circuitry, to 18 μs and 114.5 nJ for a 48-MHz XO across a temperature range of -40 °C to 90 °C. The measured steady-state power and the phase noise of the XO are 180 μW and -135 dBc/Hz at 1-kHz offset.
- 26 June 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 54 (9) , 2543-2554
Study and Design of a Fast Start-Up Crystal Oscillator Using Precise Dithered Injection and Active Inductance
This paper presents a theoretical study and design of two techniques used to reduce start-up time (T S ) and energy (E S ) of Pierce crystal oscillator (XO). An analytical study of precise injection on a crystal resonator is introduced, and based on this paper, a relaxation oscillator with a dithered frequency is designed. Next, a study of negative resistance of XO's active circuitry and a method to boost its value beyond the limit set by a crystal static capacitor are presented. A gyrator-C active inductor with high linearity is developed to accelerate the start-up process by boosting the negative resistance. A prototype integrating these techniques is fabricated in a 180-nm CMOS process and shows a significant improvement compared with the prior art. Specifically, TS and ES are reduced by 102.7× and 2.9×, compared with the XO start-up with no assisting circuitry, to 18 μs and 114.5 nJ for a 48-MHz XO across a temperature range of -40 °C to 90 °C. The measured steady-state power and the phase noise of the XO are 180 μW and -135 dBc/Hz at 1-kHz offset.
- 10 March 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 54 (6) , 1541-1552
A CMOS MedRadio Transceiver With Supply-Modulated Power Saving Technique for an Implantable Brain–Machine Interface System
A MedRadio 413-419-MHz inductorless transceiver (TRX) for an implantable brain-machine interface (BMI) in a 180 nm-CMOS process is presented. Occupying 5.29 mm 2 of die area (including pad ring), this on-off keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and S 11 of -13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42-/92-μW power from 1.8-V supply at 1/10-kbps data rates, achieving -79/-74-dBm sensitivities for 0.1% bit error rate (BER). The TX employs a current starved ring oscillator with an automatic frequency calibration loop, covering 9% supply voltage variation and 15 °C-78 °C temperature range that guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at -4-dBm output power. Wireless testing over a 350-cm distance accounting for bio-signal data transfer, multi-user coexistence, and in vitro phantom measurement results is demonstrated.
- 10 March 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 54 (6) , 1541-1552
A CMOS MedRadio Transceiver With Supply-Modulated Power Saving Technique for an Implantable Brain–Machine Interface System
A MedRadio 413-419-MHz inductorless transceiver (TRX) for an implantable brain-machine interface (BMI) in a 180 nm-CMOS process is presented. Occupying 5.29 mm 2 of die area (including pad ring), this on-off keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and S 11 of -13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42-/92-μW power from 1.8-V supply at 1/10-kbps data rates, achieving -79/-74-dBm sensitivities for 0.1% bit error rate (BER). The TX employs a current starved ring oscillator with an automatic frequency calibration loop, covering 9% supply voltage variation and 15 °C-78 °C temperature range that guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at -4-dBm output power. Wireless testing over a 350-cm distance accounting for bio-signal data transfer, multi-user coexistence, and in vitro phantom measurement results is demonstrated.
- 1 July 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2018, 4748-4751
Characterization of Stimulation Artifact Behavior in Simultaneous Electrocorticography Grid Stimulation and Recording
Bi-directional brain-computer interfaces (BCIs) require simultaneous stimulation and recording to achieve closed-loop operation. It is therefore important that the interface be able to distinguish between neural signals of interest and stimulation artifacts. Current bi-directional BCIs address this problem by temporally multiplexing stimulation and recording. This approach, however, is suboptimal in many BCI applications. Alternative artifact mitigation methods can be devised by investigating the mechanics of artifact propagation. To characterize stimulation artifact behaviors, we collected and analyzed electrocorticography (ECoG) data from eloquent cortex mapping. Ratcheting and phase-locking of stimulation artifacts were observed, as well as dipole-like properties. Artifacts as large as ±1,100 μV appeared as far as 15-37 mm away from the stimulating channel when stimulating at 10 mA. Analysis also showed that the majority of the artifact power was concentrated at the stimulation pulse train frequency (50 Hz) and its super-harmonics (100, 150, 200 Hz). Lower frequencies (0-32 Hz) experienced minimal artifact contamination. These findings could inform the design of future bi-directional ECoG-based BCIs.
- 1 July 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2018, 4748-4751
Characterization of Stimulation Artifact Behavior in Simultaneous Electrocorticography Grid Stimulation and Recording
Bi-directional brain-computer interfaces (BCIs) require simultaneous stimulation and recording to achieve closed-loop operation. It is therefore important that the interface be able to distinguish between neural signals of interest and stimulation artifacts. Current bi-directional BCIs address this problem by temporally multiplexing stimulation and recording. This approach, however, is suboptimal in many BCI applications. Alternative artifact mitigation methods can be devised by investigating the mechanics of artifact propagation. To characterize stimulation artifact behaviors, we collected and analyzed electrocorticography (ECoG) data from eloquent cortex mapping. Ratcheting and phase-locking of stimulation artifacts were observed, as well as dipole-like properties. Artifacts as large as ±1,100 μV appeared as far as 15-37 mm away from the stimulating channel when stimulating at 10 mA. Analysis also showed that the majority of the artifact power was concentrated at the stimulation pulse train frequency (50 Hz) and its super-harmonics (100, 150, 200 Hz). Lower frequencies (0-32 Hz) experienced minimal artifact contamination. These findings could inform the design of future bi-directional ECoG-based BCIs.
- 1 April 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
A CMOS inductorless MedRadio OOK transceiver with a 42 μW event-driven supply-modulated RX and a 14% efficiency TX for medical implants
An inductorless MedRadio (413~419 MHz) OOK transceiver for an implantable brain-machine interface (BMI) in 180 nm CMOS is presented. An event-driven supply modulation (EDSM) technique is introduced in the receiver to lower the power consumption to 42/92 μW at 1/10 kbps, achieving -79/-74 dBm sensitivity (at 0.1% BER). The transmitter employs a current-starved ring oscillator with an automatic frequency calibration loop, achieving 14% efficiency for random OOK data at -4 dBm output power. Wireless connection, benchtop, multi-user coexistence, and in-vitro phantom test results are demonstrated.
- 1 April 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
A CMOS inductorless MedRadio OOK transceiver with a 42 μW event-driven supply-modulated RX and a 14% efficiency TX for medical implants
An inductorless MedRadio (413~419 MHz) OOK transceiver for an implantable brain-machine interface (BMI) in 180 nm CMOS is presented. An event-driven supply modulation (EDSM) technique is introduced in the receiver to lower the power consumption to 42/92 μW at 1/10 kbps, achieving -79/-74 dBm sensitivity (at 0.1% BER). The transmitter employs a current-starved ring oscillator with an automatic frequency calibration loop, achieving 14% efficiency for random OOK data at -4 dBm output power. Wireless connection, benchtop, multi-user coexistence, and in-vitro phantom test results are demonstrated.
- 24 August 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 65 (2) , 498-509
A Silicon-Based Low-Power Broadband Transimpedance Amplifier
The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13-μm SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shunt-series feedback stage incorporating a transformer-based positive feedback; 2) an RC-degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dBΩ and an input-referred current-noise spectral density of 39.8 pA/√Hz over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm² (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).
- 24 August 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 65 (2) , 498-509
A Silicon-Based Low-Power Broadband Transimpedance Amplifier
The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13-μm SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shunt-series feedback stage incorporating a transformer-based positive feedback; 2) an RC-degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dBΩ and an input-referred current-noise spectral density of 39.8 pA/√Hz over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm² (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).
- Open Access
- 1 August 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Biomedical Circuits and Systems
- Vol. 11 (5) , 1111-1122
CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing
Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm$^{2}$ and 0.352 mm$^{2}$ of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216$\mu$ W from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19$\mu$ V$_{\text{RMS}}$ corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm$^{2}$ of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69$\mu$ W from 0.6 V supply with IRNoise of 2.3$\mu$ V$_{\text{RMS}}$ (corresponding to a PEF of 31.3) and 0.051 mm$^{2}$ of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain– computer interface systems.- 1 August 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Biomedical Circuits and Systems
- Vol. 11 (5) , 1111-1122
Open AccessCMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing
Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm$^{2}$ and 0.352 mm$^{2}$ of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216$\mu$ W from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19$\mu$ V$_{\text{RMS}}$ corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm$^{2}$ of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69$\mu$ W from 0.6 V supply with IRNoise of 2.3$\mu$ V$_{\text{RMS}}$ (corresponding to a PEF of 31.3) and 0.051 mm$^{2}$ of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain– computer interface systems. - Open Access
- 13 February 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Biomedical Engineering
- Vol. 64 (10) , 2313-2320
Performance Assessment of a Custom, Portable, and Low-Cost Brain–Computer Interface Platform
Objective: Conventional brain-computer interfaces (BCIs) are often expensive, complex to operate, and lack portability, which confines their use to laboratory settings. Portable, inexpensive BCIs can mitigate these problems, but it remains unclear whether their low-cost design compromises their performance. Therefore, we developed a portable, low-cost BCI and compared its performance to that of a conventional BCI. Methods: The BCI was assembled by integrating a custom electroencephalogram (EEG) amplifier with an open-source microcontroller and a touchscreen. The function of the amplifier was first validated against a commercial bioamplifier, followed by a head-to-head comparison between the custom BCI (using four EEG channels) and a conventional 32-channel BCI. Specifically, five able-bodied subjects were cued to alternate between hand opening/closing and remaining motionless while the BCI decoded their movement state in real time and provided visual feedback through a light emitting diode. Subjects repeated the above task for a total of 10 trials, and were unaware of which system was being used. The performance in each trial was defined as the temporal correlation between the cues and the decoded states. Results: The EEG data simultaneously acquired with the custom and commercial amplifiers were visually similar and highly correlated (ρ = 0.79). The decoding performances of the custom and conventional BCIs averaged across trials and subjects were 0.70 ± 0.12 and 0.68 ± 0.10, respectively, and were not significantly different. Conclusion: The performance of our portable, low-cost BCI is comparable to that of the conventional BCIs. Significance: Platforms, such as the one developed here, are suitable for BCI applications outside of a laboratory.
- 13 February 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Biomedical Engineering
- Vol. 64 (10) , 2313-2320
Open AccessPerformance Assessment of a Custom, Portable, and Low-Cost Brain–Computer Interface Platform
Objective: Conventional brain-computer interfaces (BCIs) are often expensive, complex to operate, and lack portability, which confines their use to laboratory settings. Portable, inexpensive BCIs can mitigate these problems, but it remains unclear whether their low-cost design compromises their performance. Therefore, we developed a portable, low-cost BCI and compared its performance to that of a conventional BCI. Methods: The BCI was assembled by integrating a custom electroencephalogram (EEG) amplifier with an open-source microcontroller and a touchscreen. The function of the amplifier was first validated against a commercial bioamplifier, followed by a head-to-head comparison between the custom BCI (using four EEG channels) and a conventional 32-channel BCI. Specifically, five able-bodied subjects were cued to alternate between hand opening/closing and remaining motionless while the BCI decoded their movement state in real time and provided visual feedback through a light emitting diode. Subjects repeated the above task for a total of 10 trials, and were unaware of which system was being used. The performance in each trial was defined as the temporal correlation between the cues and the decoded states. Results: The EEG data simultaneously acquired with the custom and commercial amplifiers were visually similar and highly correlated (ρ = 0.79). The decoding performances of the custom and conventional BCIs averaged across trials and subjects were 0.70 ± 0.12 and 0.68 ± 0.10, respectively, and were not significantly different. Conclusion: The performance of our portable, low-cost BCI is comparable to that of the conventional BCIs. Significance: Platforms, such as the one developed here, are suitable for BCI applications outside of a laboratory.
- 1 August 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2016 (1557170X) , 4491-4494
Feasibility of an ultra-low power digital signal processor platform as a basis for a fully implantable brain-computer interface system
A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, and subsequently using human electroencephalogram (EEG) during eyes opening and closing task. On average, the system spent 322 ms to process and analyze 2 s of data. Crosstalk (<;-65 dB) and harmonic distortion (~1%) were minimal. Timing jitter averaged 49 μs per 1000 ms. The online BCI decoding accuracies were 100% for both function generator and EEG data. These results show that a complex BCI algorithm can be executed on an ULP DSP without compromising performance. This suggests that the proposed hardware platform may be used as a basis for future, fully implantable BCI systems.
- 1 August 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2016 (1557170X) , 4491-4494
Feasibility of an ultra-low power digital signal processor platform as a basis for a fully implantable brain-computer interface system
A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, and subsequently using human electroencephalogram (EEG) during eyes opening and closing task. On average, the system spent 322 ms to process and analyze 2 s of data. Crosstalk (<;-65 dB) and harmonic distortion (~1%) were minimal. Timing jitter averaged 49 μs per 1000 ms. The online BCI decoding accuracies were 100% for both function generator and EEG data. These results show that a complex BCI algorithm can be executed on an ULP DSP without compromising performance. This suggests that the proposed hardware platform may be used as a basis for future, fully implantable BCI systems.
- 1 August 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2016 (1557170X) , 2776-2779
A small, portable, battery-powered brain-computer interface system for motor rehabilitation
Motor rehabilitation using brain-computer interface (BCI) systems may facilitate functional recovery in individuals after stroke or spinal cord injury. Nevertheless, these systems are typically ill-suited for widespread adoption due to their size, cost, and complexity. In this paper, a small, portable, and extremely cost-efficient (<;$200) BCI system has been developed using a custom electroencephalographic (EEG) amplifier array, and a commercial microcontroller and touchscreen. The system's performance was tested using a movement-related BCI task in 3 able-bodied subjects with minimal previous BCI experience. Specifically, subjects were instructed to alternate between relaxing and dorsiflexing their right foot, while their EEG was acquired and analyzed in real-time by the BCI system to decode their underlying movement state. The EEG signals acquired by the custom amplifier array were similar to those acquired by a commercial amplifier (maximum correlation coefficient ρ=0.85). During real-time BCI operation, the average correlation between instructional cues and decoded BCI states across all subjects (ρ=0.70) was comparable to that of full-size BCI systems. Small, portable, and inexpensive BCI systems such as the one reported here may promote a widespread adoption of BCI-based movement rehabilitation devices in stroke and spinal cord injury populations.
- 1 August 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2016 (1557170X) , 2776-2779
A small, portable, battery-powered brain-computer interface system for motor rehabilitation
Motor rehabilitation using brain-computer interface (BCI) systems may facilitate functional recovery in individuals after stroke or spinal cord injury. Nevertheless, these systems are typically ill-suited for widespread adoption due to their size, cost, and complexity. In this paper, a small, portable, and extremely cost-efficient (<;$200) BCI system has been developed using a custom electroencephalographic (EEG) amplifier array, and a commercial microcontroller and touchscreen. The system's performance was tested using a movement-related BCI task in 3 able-bodied subjects with minimal previous BCI experience. Specifically, subjects were instructed to alternate between relaxing and dorsiflexing their right foot, while their EEG was acquired and analyzed in real-time by the BCI system to decode their underlying movement state. The EEG signals acquired by the custom amplifier array were similar to those acquired by a commercial amplifier (maximum correlation coefficient ρ=0.85). During real-time BCI operation, the average correlation between instructional cues and decoded BCI states across all subjects (ρ=0.70) was comparable to that of full-size BCI systems. Small, portable, and inexpensive BCI systems such as the one reported here may promote a widespread adoption of BCI-based movement rehabilitation devices in stroke and spinal cord injury populations.