Takayuki Kawahara

The importance of the role of two-level fluctuators (TLFs) in causing qubit frequency (f_q) shifts has been highlighted in previous studies to improve the gate fidelity in silicon spin qubits at higher temperatures. In this study, we employed a simulation technique to investigate the origin of the temperature dependence of f_q shifts in silicon spin qubits. Among the various possible microscopic origins, we focused on the charge noise, which is attributed to the TLFs at the semiconductor/oxide interface, for which the experimental features of the f_q shift have been theoretically reproduced in previous studies. We analyze the TLF characteristics required to improve the gate fidelity by simulating the effect of charge noise, considering the spatial and energetic distributions, as well as characteristic parameters. We observed that the exponential distribution of the activation energies was preferable for reproducing the f_q shift and fidelity improvement. Moreover, in terms of parameter selection, a short transition time and a steep temperature transition can improve fidelity during higher-temperature operations. Based on these findings, we discussed the origin of TLFs and observed that electronic transitions are more likely to produce TLFs than transitions involving atomic displacement.

Annealing processors (APs), which can efficiently solve combinatorial optimization problems (COPs), have attracted attention. APs that have fully-coupled spin coupling are the focus of active research due to their ability to handle a wide range of COPs. However, since a single spin is updated by referring to the states of all other spins, sequential spin updates are necessary. This makes it difficult to achieve both faster computation time and stable solution quality. We propose transition-based multi-state pseudo annealing (TMSPA), which is an annealing method that enables discrete spin states between ±1 and maps the conventional two spin states to different transition directions. By using TMSPA, we solved the Max-cut problem and the traveling salesman problem (TSP). We found that TMSPA enables all-parallel annealing for both COPs. In terms of solution quality, TMSPA performed comparably to or better than simulated annealing and pseudo annealing. For the TSP, TMSPA reached better minimum values with less than one-third the number of Monte Carlo steps than previous all-parallel annealing methods. We also propose an all-parallelized annealing processing system using TMSPA. By using the proposed system with 1024- and 2048-spin configurations, we achieved better solution quality and 6.25 times faster computation time while operating at half the frequency and limiting the increase in circuit-resource utilization to 1.03–5.70 times compared with a previous parallelized AP. This result indicates that reducing circuit complexity using TMSPA is highly effective in the implementation of parallelized APs.

Annealing processors (APs) specialized for solving combinatorial optimization problems (COPs) have been gaining attention. Among them, APs that use a fully-coupled Ising model are in demand because of their versatility. However, due to the complexity of the spin couplings, challenges remain in achieving systems that balance both capacity (number of spins) and precision (interaction bit width). Previous studies have implemented annealing systems that only increase the number of spins using a scalable structure by distributing the calculation across multiple chips. This study proposes a dual scalable annealing processing system (DSAPS) that can simultaneously scale both capacity and precision using the same scalable structure. This demonstrates a new direction that combines both the number of spins and interaction bit width. A board implementation utilized spin threads to create two types of DSAPS: DSAPS #1, with 2048 spins, 10-bit interactions and four threads, and DSAPS #2, with 1024 spins, 37-bit interactions and two threads. Scaled MAX-CUT problems were used for operational validation, achieving an accuracy of over 99% compared with theoretical values. In another validation using the 0-1 knapsack problem, DSAPS #1 achieved an average deviation of over 99% relative to the knapsack capacity, whereas DSAPS #2 reduced the average deviation to 0.73%. This result is close to the average deviation of 0.40% obtained with an annealing emulation on a CPU (64-bit), demonstrating the significance of implementing DSAPSs suited to the characteristics of COPs.

To build Neural Networks (NNs) on edge devices, Binarized Neural Network (BNN) has been proposed on the software side, while Computing-in-Memory (CiM) architecture has been proposed on the hardware side. For use on CiM architecture-based BNN, Magnetic Random Access Memory (MRAM) has been attracting interest thanks to its low power consumption and fast write operation. In this study, we propose a new BNN training algorithm utilizing ternarized gradients (TGBNN) for MRAM-based CiM architecture to enable both training BNN and inference on edge devices. TGBNN has only ternary gradients, binary weights, binary activations, binary inputs in both training and inference phases. In other words, real-valued weights and real-valued gradients, which are necessary on conventional BNNs in the training phase, never appear on our BNN. TGBNN uses three key techniques: ternarized gradients, improved straight through estimator, and stochastic weights update. In addition, to build TGBNN on edge devices, we propose a new MRAM-based CiM architecture. Our MRAM array consists of an MRAM cell-based XNOR gate utilizing Voltage Controlled Magnetic Anisotropy (VCMA) and MRAM cell-based stochastic updating utilizing Spin Orbit Torque (SOT). Owning to our MRAM-based CiM architecture, we can halve the scale of the Multiply-and-Accumulate (MAC) operation circuit in comparison with the conventional method. Lastly, we evaluated TGBNN on our MRAM utilizing the MNIST handwriting dataset. The result showed that the accuracy of TGBNN was only 0.92 % lower than that of regular BNN has the same structure, and the training of TGBNN can converge faster than it of regular BNN. In addition, we found 88.28 % accuracy with ECOC-based learning TGBNN. Therefore, we can build a BNN on the edge side in both inference and training phases owning to TGBNN on our MRAM-based CiM architecture.

The development of annealing processors has progressed as a solution to large-scale combinatorial optimization problems. Inside a fully-coupled annealing machine that can handle a wide range of combinatorial optimization problems, there are elements called interactions that indicate the force between spins, the number of which is the square of the number of spins. However, the area of the circuit is greatly restricted. Therefore, we focus on the symmetry of interactions and propose a method for reducing the number of interactions by giving regularity to the two-dimensional arrangement of interactions. The interaction halving method has a high affinity with the previously published scalable fully-coupled annealing machine, and the interaction proposed this time for the 384-spin full-coupled annealing machine using 16 Field Programmable Gate Array chips shown in previous research. By applying the reduction method, we succeeded in implementing two independent 384-spin fully coupled annealing machines with 16 chips.

To achieve quantum computing using semiconductor spin qubits, the spin qubits must be precisely controlled. However, unexpected noise limits this precision and prevents the implementation of error correction codes. Specifically, frequency shifts have been found to suppress one-qubit gate fidelity. Although the exact source of the frequency shifts remains unclear, several experiments have indicated a relationship between the frequency shift and heating from the control signal. Based on these results, we modeled the heating effect using the low-temperature dependence of specific heat from the Debye model to simulate qubit control with frequency shifts. This model quantitatively reproduces some of the experimental results and makes it possible to simulate qubit gates with temperature-dependent frequency shifts. The simulated control fidelity of the proposed model was consistent with the experimental results, demonstrating that a gate fidelity above $99.9$% can be achieved in a hot environment. Additionally, our comparison of the two temperature-dependent frequency shift models reveals the condition for a microscopic frequency shift model in which the variance of the frequency shift is limited to a specific range. Furthermore, we investigated gate fidelity using the DRAG method and demonstrated the utility of temperature-dependent simulations.

Annealing processors specialized for combinatorial optimization problems are attracting attention. Although a general-purpose fully-coupled type is required for annealing processors in CMOS, the complexity of the coupling has led to scalability issues. Therefore, a scalable structure has been proposed that divides the calculation into multiple chips and has already been verified by using FPGAs. In the proposed system, 4,096 spins are implemented on a single board by 36 22-nm CMOS LSIs (512-spin fully-coupled annealing processor) and 1 FPGA for control. This is the largest fully-coupled annealing processing system implemented on a single board. This paper describes two main techniques used in the proposed system. The first is an approximate halving of the number of chips (from 64 to 36) by reducing the interaction matrix, and the second is an 8-parallel-solution search by parallel operation after reducing the number of chips. We found that a single LSI and a control FPGA can operate as a 512-spin fully-coupled annealing processor. Compared with CPU, the proposed system with 36 LSIs and control FPGAs improves computation speed by a factor of 34.0 and power performance by a factor of 2,344, while searching for 8 solutions in parallel.

We propose a bi-directional read method for improving read-disturbing resistance to maintain high read reliability of spin-orbit-torque magnetoresistive random-access memory. Since this method can withstand magnetization switching with a current 10 times or more that of the conventional method, it enables low power consumption operation while maintaining high read reliability. We evaluated our method in terms of improving read disturbance resistance by focusing on, the dependence of material properties, size, and wiring resistance in the memory cell array. We also evaluated the read reliability as a chip to confirm the method's effectiveness.

We propose a read-reliability model to construct a bi-directional stabilized spin-orbit-torque magnetoresistive random access memory (SOT-MRAM) structure. Since this model withstands magnetization switching with ten times the current compared with the conventional SOT-MRAM structure, it enables low power-consumption operation while maintaining read reliability. We used various materials with different axes of easy magnetization as ferromagnetic materials in the proposed model and confirmed that all the materials had disturbance reduction of ten times or more. The magnitude of the coercive force of the ferromagnetic material affected this reduction. We also evaluated the effectiveness of the proposed model regarding disturbance reduction for various device shapes and found there were differences in this effectiveness because the behavior of magnetization switching differs depending on the shape and that vortex magnetization affects the model. However, considering the array configuration of the proposed model, the number of memory cells was limited to about 1000; therefore, a more optimal configuration is required.