Atif Raza Jafri

Superconducting qubits are pivotal in advancing quantum computing, poised for scale but limited by the complexity and fidelity of their control and readout systems, relying on RF and signal processing infrastructure. This survey serves as a comprehensive and technically grounded review of control and readout architectures tailored for superconducting qubits. Synthesizing insights from device physics, circuit design, microwave engineering, signal processing, and cryogenic integration, this work details the practicalities of RF pulse generation, signal synthesis, and readout signal analysis for quantum systems. it covers key requirements, parameters, and pulse engineering techniques, including commonly used envelopes like Gaussian and DRAG designs. Moving to the system level, this survey systematically classifies and critically analyses current architectural strategies (covering key areas like frequency conversion, waveform management, and system infrastructure) and technology platforms (including adaptive classical control stacks, cryogenic CMOS circuits, and novel interconnects and interfaces), evaluating their trade-offs in performance. Extensive literature analysis identifies prevailing limitations such as wiring complexity, thermal budget constraints, latency, and power consumption, while highlighting underexplored opportunities for on-chip signal processing and novel interconnects, drawing analogies to advanced communication systems design. By consolidating diverse control paradigms and critically evaluating their trade-offs, this survey provides a unified foundation for designing next-generation quantum control stacks. Finally, a forward-looking roadmap outlines key trends in monolithic integration, cryo-compatible digital architectures, and physics-informed hardware co-design, offering both a retrospective synthesis and a prospective vision for quantum hardware engineering beyond the NISQ era.

An efficient hardware implementation of correlated Rayleigh fading channel simulator is presented in this paper. It emulates Doppler effects based on the use of Overlap-Save (OLS) method. OLS is used for both, the fading variates generator and the time domain interpolator, leading to a scalable complete solution. Moreover, additional simplifications were introduced to reduce even further algorithmic complexity when compared with the original OLS-based proposal. An efficient hardware implementation is achieved through maximizing the utilization rate of allocated hardware resources. When added to its scalability, this makes the proposal appealing to emulate channels with multipath effects for MIMO systems. Indeed, the proposed parallel architecture enables a throughput of 34 Mega Samples per Second per path at a clock frequency of 275 MHz on Xilinx Virtex-7 FPGA. The achieved throughput allows the support of the most demanding LTE configuration with 20 MHz channel bandwidth. To the best of our knowledge, this is the first ever real-time hardware implementation of OLS-based channel emulator.

Parallel-connected uninterruptible power supply (UPS) systems have been used to maintain power supply to the critical load in order to increase power capacity and system reliability. This paper presents a robust and precise voltage control strategy for parallel-connected UPS systems. Each parallel-connected UPS system consists of a three-phase inverter with an output inductor-capacitor (LC) filter directly connected to an AC common bus in order to feed the critical load. Fractional-order sliding mode control (FOSMC) is proposed to maintain the quality of the output voltage despite linear, unbalanced and/or nonlinear load condition. The Riemann-Liouville (RL) fractional derivative is employed in designing the sliding surface. The voltage control strategy effectively eliminates the parametric uncertainties, external disturbances, and reduce the total harmonic distortion (THD) of the output voltage. Furthermore, it also maintains very good voltage regulation such as dynamic response and steady-state error under the nonlinear or unbalanced load conditions. The stability of the proposed controller is proven by applying Lyapunov stability theory. Droop control approach and virtual output impedance (VOI) loop are investigated to guarantee the accurate active and reactive power-sharing for parallel-connected UPS system. Finally, the implementation of the control scheme is carried out by using MATLAB/Simulink real-time environment.

Universal filtered multicarrier (UFMC) is a low complexity promising waveform that provides quasi‐orthogonal property among subcarriers. In addition, it can achieve much better out‐of‐band emission performance than orthogonal frequency division multiplexing (OFDM) system. Authors have proposed a hardware platform to implement a UFMC transmitter in this paper. Highly reduced complexity schemes for IFFT, filtering, and spectrum shifting are realized on actual hardware. This helps to achieve overall architecture of the transmitter at the cost of minimal FPGA resource usage. Hence, the overall design uses only 1038 slice registers, 1154 slice LUTs, and 64 multipliers of Xilinx Virtex‐7 XC7VX330t device. A throughput of 773.5 Msamples/sec at an operational frequency of 364 MHz is achieved. This throughput is adequate for processing 50 Physical Resource Blocks (PRB) of LTE 10 MHz channelization in required time. The presented architecture provides a latency of only 2% of one LTE 10MHz channelization symbol due to the implementation of pipelining at different levels. Although the presented hardware design in its current form meets LTE 10MHz channelization throughput requirements, further increase in throughput is possible due to the scalable nature of the architecture. To the best of our knowledge, this work is first ever FPGA solution for UFMC transmitter presented in the literature.

The inclusion of machine-type communication in the 5G technology has motivated the research community to explore new derivative waveforms of orthogonal frequency division multiplexing. Filter bank multicarrier, universal filtered multicarrier (UFMC), and generalized frequency division multiplexing techniques are under evaluation with respect to their suitability to 5G requirements. In addition to acceptable spectral performance, investigation on computational complexity reduction while addressing flexibility can help in the selection of suitable waveform among multiple options available for 5G. In this regard, based on analysis of computation involved in UFMC waveform construction, few reduced complexity solution for UFMC transmitter implementations are recently proposed. However, hardware-implementation-related issues have not been discussed in detail. In this paper, we have proposed reduced complexity hardware solutions for all three constituent blocks, i.e., inverse discrete Fourier transform (IDFT), finite impulse response (FIR) filter, and spectrum shifting blocks of a UFMC transmitter. For IDFT part, a reduced complexity IFFT solution using Radix-2 decimation in a time technique is presented, where more than 42% computations can be avoided. It is also shown that how five times less number of multipliers can be used in an FIR filter to simplify filter architecture. Finally, a highly efficient method is presented to compute spectrum shifting coefficients through small sized lookup table.

Applying rotated and cyclic Q delayed (RCQD) modulation on the transmitter side improves the performance of the receiver in case of fading channel conditions along with erasures. However, the complexity of demapping in the receiver increases significantly to achieve this elevated performance. Many low complexity demapping solutions are available but few are actually implemented in hardware. Recently, new constellation rotation angles and associated simplified demapping technique with better performance for fading channel conditions along with erasure scenarios has been proposed. In this paper, we propose a novel demapper architecture model that exploits these latest simplifications. Moreover, a joint demapper implementation is proposed which can demap the symbols from different constellations using full or simplified demapping algorithm to achieve best throughput in terms of LLR/sec. Compared to state-of-theart implementations of RCQD demappers, significant hardware reductions are demonstrated encouraging the use of RCQD modulation in future wireless communication applications.