Eduard Bertran

A novel Doherty-like power amplifier (DPA) has been fabricated using 15 W, 2.7 GHz, GaN HEMT transistors. The quarter-wave transformer used in the classical DPA topology is replaced by a matching network including a Klopfenstein taper. From a practical prototype realization, this modification has demonstrated that the resulting DPA bandwidth (BW) is increased in comparison with the conventional topology while keeping the efficiency figures. Moreover, this design allows an easy tuning of the group delay through the output reactance of the taper, resulting in a more straightforward adjustments than other recently-published designs where the quarter-wave transformer is replaced by multi-section transmission lines (hybrid or similar). Experimental results have shown an average efficiency of 47.2% for the HSPA + modulation centered at 2.25 GHz.

This paper presents a wideband GaN Doherty power amplifier (DPA) in the 2.6 GHz band with a 3 stages Wilkinson splitter where the impedance inverter is based on a tapered line instead of a quarter wave transformer. From the comparison with the same amplifier using a typical quarter-wave transformer as impedance inverter, and keeping both designs the same bandwidth (1.6 to 3.3 GHz, 65% of the fractional bandwidth), the Power Added Efficiency (PAE) is enhanced up to 50% (from 40.46% to 61.17% at 35 dBm input power) in the DPA with a tapered line. Besides, the transducer gain remains practically unaltered.

This paper presents how to apply order reduction in wide-band digital predistortion (DPD) linearizers using the principal component analysis (PCA) technique. This method is tested in a wireless backhauling transmitter where four 28 MHz adjacent subcarrier transmission of M-QAM signals are considered. The DPD has to counteract not only the PA nonlinear behavior, but also its dynamics. This may results critical when considering wideband signals since the number of coefficients required to model memory effects can grow dramatically. By applying the PCA technique, the number of essential parameters can be significantly reduced. In addition, a strategy to minimize the computational cost of finding the optimal coefficients is also presented. A test-bed for evaluating the DPD linearization performance of the RF subsystem when PCA is applied was deployed and experimental results are presented in this paper.

This paper presents the design of a nonlinear autoregressive moving average (NARMA) digital adaptive predistorter (DAPD) for power amplifier (PA) linearization consisting of a low-complex closed-loop architecture. Both the predistortion function and the adaptation algorithm are fully implemented in a field-programmable gate array (FPGA) device, without the need for using any additional coprocessor. The proposed predistortion architecture is capable to compensate for both the PA nonlinear distortion and memory effects. Moreover, this DAPD allows almost real-time adaptation without interrupting the normal transmission. The computational complexity introduced by this DAPD is studied in this paper. The proposed theoretical design is implemented in an FPGA, whereas the linearization performance of the DAPD is validated through simulated and experimental results.

Summary form only given, as follows. This paper presents a new digital predistorter (DPD) to compensate for nonlinear distortion present in Envelope Tracking (ET) Power Amplifiers (PAs) driven by slew-rate limited versions of the real signal's envelope. Unfortunately, the use of slower versions of the real signal's envelope generates nonlinear memory effects. This paper shows experimental results that prove that is possible to compensate for these nonlinear memory effects.

This paper shows a method for generating slew-rate limited envelopes in order to accomplish the slew-rate restrictions of the envelope driver in envelope tracking transmitters. The proposed algorithm can run in real-time and it is implemented in a digital front-end of a Software Radio system. Simulation results and conclusions are provided to validate the methodology. Moreover, experimental results of an FPGA implementation are also provided.

This paper assesses the PAPR for multimode transmitters (WiMAX, WiFi and Bluetooth), considering different combinations of modulations and access techniques (spreading codes and OFDM). Simulations include preamble, header and data fields. Results give hints for tailoring the back-off of power amplifiers, as well as for foreseeing the necessary slew-rate in polar transmitters.

This paper presents an exhaustive description of a field programmable gate-array (FPGA) based set-up for envelope tracking and dynamic biasing of RF power amplifiers (PA). The system includes digital adaptive predistortion (DAPD) and gain compensation deployed in a FPGA device. For testing purposes a GaN HEMT RF PA operating at 3.5 GHz was considered. Preliminary experimental results are provided showing the DAPD compensate for the steady-state PA nonlinear distortion arising as a consequence of varying the power supply.

This article performs an analysis of current limitations regarding the extraction of parallel behavioral models to reproduce the power amplifier (PA) nonlinear behavior and its dynamics. To overcome these limitations, a general preprocessing block that clearly improves the identification capabilities shown by classical parallel structures is proposed. It follows the principle of separating both static and dynamic nonlinear behavior of the PA to obtain a better identification performance. A comparison with common parallel configurations using linear estimation is performed, to highlight the benefits of using the preprocessing structure. Furthermore, a new nonlinear parallel structure using sub-band filtering techniques is also proposed. For the models extraction and comparison, four types of noise-free simulated data presenting different levels of nonlinearities and memory, as well as a measured signal obtained from a laboratory amplifier have been considered. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.