Pedro Julian

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In this work a compact model for square planar inductors printed on flexible substrate is proposed. The approach considers the deformation of the metal traces of square spiral inductors when the substrate is subjected to physical stretch. The model considers a typical pi-network for the device, where each component is calculated for different stretching values adapting widely accepted models on the literature for the total inductance, the AC resistance and the ground coupling and inter-wounding capacitances. Model results are contrasted to 3D full electromagnetic wave simulations under parametric sweeps of the dimensions calculated under stretch. Results show good agreement within a 20 % stretch up to the first resonance frequency of the structure. The model can prove useful for the optimization of component design for printed applications on flexible substrates.

We discuss the architecture, implementation and testing of a simplicial Cellular Neural Network (CNN) vector processor core aimed at vision oriented intelligent Internet-of-Things (IoT) devices. The architecture comprises a linear array of 64 processing elements (PE), each connected to a 4 neighbor clique operating on 8-bit input and state data. A 3-bit simplicial parameter, allows multilevel function approximation and extends the functionality over previously reported chips. Input data vectors are stored in two 64 x 64 x 8-bit data caches. The chip is synthesized from a custom designed ultra low voltage CMOS library and fabricated in a 55nm CMOS technology. Dynamic voltage/frequency scaling allows operation at power supplies between 0.5 and 1.2 Volts allowing for a tradeoff between speed and power. The fabricated chip achieves an overall performance of 7.05 TOPS/W at 732fps, with a dynamic energy efficiency of 12.2fJ per operation (OP) at 1.2 Volts.

This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece‐wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight‐neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low‐voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.

Welcome to this Special Section, a collection of selected papers presented at the 2016 IEEE Latin American Symposium on Circuits and Systems (LASCAS 2016), held in Florianópolis, Brazil, from February 28 to March 2, 2016. Over 250 delegates attended the conference, where 100 papers were presented, selected from 203 papers submitted across 20 tracks.

The design of a true Bernoulli Random Number Generator (RNG) source with a true probability p = 0.5 is a challenging problem. In this work, we present a novel design of a True RNG (TRNG) that achieves a true E(p(n)) = 0.5. The architecture is based on the perturbation of a Sigma-Delta modulator using random telegraph noise (RTN).

In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture implements a variety of processing algorithms classes ranging from convolutional networks (Con-vNets) to linear and non-linear morphological processing, probabilistic inference using exact and approximate Bayesian methods and ConvNet based classification. The processing pipeline is implemented entirely using event based neuromorphic and stochastic computational primitives. The system is capable of processing in real-time 160 × 120 raw pixel data running on a reconfigurable computing platform (5 Xilinx Kintex-7 FPGAs). The reconfigurable computing implementation was developed to emulate the computational structures for a 3D System on Chip (3D-SOC) that will be fabricated in the 55nm CMOS technology and it has a dual goal: (i) algorithm exploration and (ii) architecture exploration.