Diego Calvo Ruiz

The present paper shows a new fixed abrasive bond-grit formulation aimed for best-in-class, low-cost and high-quality finished SiC wafer surfaces. Grinding wheels manufactured with this technology can accomplish ultra-smooth SiC (Ra = 0.55 nm and TTV < 1 μm) surfaces due to their unique bonding structure and their tailored grit size. Additionally, SiC wafers ground with these wheels exhibit reduced sub-surface crystal damage, mirror-like polished surface and improved wafer geometry while both the grinding forces and the wheel wear are kept low.

Indium phosphide (InP)‐based high electron mobility transistors (HEMTs) with an offset gate enable higher maximum oscillation frequency (f_MAX) values because of the resulting reduction in gate‐to‐source resistance. Following this approach, improved direct current (DC) characteristics and cutoff frequencies (f_T/f_MAX > 410/710 GHz with L_G = 50 nm) are shown with respect to centered gate devices. However, HEMTs with an offset gate show degraded noise performances compared with centered gate devices because of a higher gate leakage current. The results show that offsetting the gate closer to the source is not desirable for ultra‐low‐noise performance.

GaInAs-based Metal Oxide Semiconductor High Electron Mobility Transistors (MOS-HEMTs) can in principle combine the wide bandwidth of HEMTs to the low gate leakage current of MOSFETs in a single deeply-scaled ultrahigh speed low-noise technology. Despite advances in the fabrication of MOS-HEMT devices and MMICs, the transistor microwave noise properties of GaInAs MOS-HEMT devices have not yet been reported. In the present study, the room temperature DC and wideband RF noise properties (8-50 GHz) of GaInAs channel MOS-HEMTs are characterized and contrasted to those of a 50 nm low-noise HEMT with the same channel composition/thickness and similar fT: at a given bias VDS = 0.5 V, the HEMT provides lower minimal noise figures (NFMIN) and higher associated gain. In contrast to HEMTs, the MOS-HEMTs particularly suffer from lower frequency noise contributions attributed to enhanced impact ionization. Remarkably, operation at VDS = 0.4 V to mitigate ionization enables MOS-HEMTs to match the HEMT wideband NFMIN performance despite a significantly poorer low-field channel mobility. The present MOS-HEMTs show the highest reported maximum oscillation frequency fMAX = 637 GHz for a measured gate length LG = 33 nm and a (2 × 15) μm width. Gate annealing is shown to be deleterious to the MOS-HEMT DC and noise properties.

Impact ionization negatively affects transistor noise properties at low and mm-wave frequencies. We show that composite InAs/GaInAs channels with thin InP sub-channels can be engineered to greatly suppress impact ionization and achieve improved noise properties while maintaining excellent HEMTs cutoff frequencies (f T /f MAX > 410/660 GHz with L G = 50 nm). This is the first demonstration of high-performance HEMTs combining InAs channel insets with InP sub-channels. HEMTs with a 3 nm InAs inset and an InP sub-channel outperform designs relying on 5 nm InAs insets in f T /f MAX metrics at higher drain biases and currents, as well as in low-noise performance. At 40 GHz, the 3 nm InAs inset HEMT shows NFMIN = 0.65 dB (compared to 0.93 and 1.15 dB for the 5 nm InAs inset HEMTs, with and without InP sub-channel, respectively). We extract the "impact ionization transconductance" g im from S-parameter measurements to quantify and map impact ionization levels over the I DS -V DS domain for the first time, clearly showing a delayed onset to higher V DS and I DS values in the optimized channel design (3 nm InAs inset with an InP sub-channel).

InP-based HEMTs with composite GaInAs/InAs channels are recognized for their high frequency performance thanks to their superior carrier transport properties. On the other hand, the addition of an InP subchannel to a GaInAs channel can effectively suppress channel impact ionization, lower the output conductance, and improve noise properties. Although the literature provides a number of reports about both separate approaches, we merge both strategies in the present study and report the first GaInAs/InAs/InP composite channel HEMTs. The influence of the InAs inset location is studied through DC, RF and noise characterization. Devices with the InAs inset located further from the top AlInAs barrier exhibit an improved minimum noise figure NFMIN due to a reduced gate leakage current. The NFMIN improvement is accompanied by a slight degradation in both the output characteristics and cutoff frequencies resulting from the increased average gate-to-2DEG separation. Our results indicate that the combination of an InAs inset and an InP subchannel opens promising HEMT design avenues for broadband low-noise applications.

GaInAs/InAs composite channels in InP-based pHEMTs enable wideband and/or low-noise performances because of their superior carrier transport properties. To date, the influence of the InAs inset design details on transistor performance has not been parametrized in the literature. We present a systematic study of the effects of the InAs channel inset thickness on transistor characteristics and cutoff frequencies versus temperature, and on the noise performance at 300 K. The epitaxial layer structures considered here incorporate 2 to 5-nm InAs insets in a fixed total composite channel thickness. All layers exhibit excellent electron mobilities (from 40,200 to 54,800 cm²/Vs at 77 K). Thicker InAs insets improve both the current gain cutoff frequency (fT) and the maximum oscillation frequency (fMAX). However, they also result in higher gate leakage currents and increased channel impact ionization. 50-nm gate length pHEMTs with a 5-nm InAs inset feature the highest simultaneous fT/fMAX ≥ 390/675 (455/800) GHz at 300 (15) K for a low-noise bias but exhibit the poorest minimum noise figure NFMIN. Whereas higher fT (and/or fMAX) values have traditionally been associated with improved noise performances, this is no longer the case.

Optimum device performance in terms of noise and gain of AlInAs/GaInAs/InP High Electron Mobility Transistors (HEMTs) requires minimizing the contact resistance RC. In several HEMT fabrication steps in device manufacturing it is common to expose highly-doped semiconductors layers to heated solvents for prolonged periods of time. It is shown here that even a small amount of water or water vapor present during photoresist removals, metal lift-offs or related processes can dramatically affect the final device performance by promoting electrochemical etching of the semiconductor layers adjacent to metal stacks. In this paper, the impact of metal lift-off on erosion of HEMT epitaxial layers and Ohmic contact resistance is studied with respect to different layer doping levels, compositions and metal stacks forming the Ohmic contacts.

A Pt/Ti/Pt/Au gate electrode stack is commonly used in AlInAs/GaInAs/InP high electron mobility transistors (HEMTs) due to the high Schottky barrier height of Pt on AlInAs and the fact that Pt can be controllably diffused through semiconductor layers thereby enabling vertical scaling. We show here that the Pt-AlInAs reaction is not only controlled by the annealing time and temperature — the annealing ambient and the thermal ramp rate also affect the diffusion of Pt through the underlying semiconductor layers and impact the DC and RF device performance. Following the gate metal deposition, one process split was rapid thermal annealed (RTA) at 250°C and subsequently passivated by atomic layer deposition (ALD) at 180°C. For the second process split, the Pt gate sink-in process was carried out in the ALD system at 250°C simultaneously with the gate passivation. Despite identical gate sink-in temperatures, the two process splits exhibit different characteristics suggesting different gate-to-channel distances. The distance of the Pt gate to the GaInAs channel was therefore confirmed through high-resolution cross-sectional scanning transmission electron microscopy (STEM) analysis. The results presented here reveal that both the suitable ramp rate and the sink-in ambient are necessary to achieve a fully sunken Pt gate.