Daeseok Lee

Proton-based electrochemical random-access memory (H-ECRAM) has attracted attention as a promising emerging memory for neuromorphic computing due to its analog conductance modulation and high energy efficiency. Atomic layer deposition (ALD) is attractive due to its excellent conformality and scalability. However, the inherently high density of ALD-grown electrolyte films limits ionic transport, leading to degraded switching performance of H-ECRAM. In this work, we address this issue by engineering the density of ZrO ₂ electrolytes through low-temperature ALD. By reducing the deposition temperature, the film density is effectively decreased and density-controlled ZrO ₂ electrolyte exhibits significantly improved ionic mobility. It contributes to a substantial enhancement in switching characteristics, such as larger conductance modulation, an improved on/off ratio, and enhanced weight update linearity. These results show a feasibility that density-controlled ALD electrolyte can offer potential for scalable and high-performance neuromorphic hardware.

Pb-free double perovskite Cs2CuBiBr6 (CCBB)-based resistive random-access memory (ReRAM) synaptic devices are developed using a dual-interface engineering approach to achieve stable resistive switching and neuromorphic functionality. High-quality CCBB thin films are obtained via optimized antisolvent-assisted crystallization, enabling enhanced crystallinity and reduced defect-induced energetic disorder. Modification of the bottom interface with a poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) interlayer improves CCBB film continuity and provides a more favorable environment for homogeneous charge injection. The introduction of an ultrathin bathocuproine (BCP) interlayer at the top interface regulates the spatial redistribution of Ag-related species. The cooperative regulation of charge injection and Ag-related electro-ionic processes promotes more reproducible formation and rupture of localized conductive pathways, resulting in improved switching stability and device-to-device reproducibility. The CCBB-based ReRAM exhibits reliable bipolar resistive switching over 600 cycles, an on/off current ratio of approximately 103, and stable data retention up to 104 s. Gradual and repeatable conductance modulation under electrical pulse stimulation further demonstrates synaptic potentiation and depression behaviors. MNIST-based neural network simulations reveal excellent neuromorphic performance, with up to 90% recognition accuracy. This work highlights cooperative dual-interface regulation of charge injection and Ag-related electro-ionic processes as an effective design strategy for achieving reliable Pb-free perovskite ReRAM and neuromorphic synaptic operation.

This study presents a compact neuron device based on a PN heterojunction neuron to enable hardware-level deep neural networks (HDNNs) with improved integration density beyond the limits of complementary metal-oxide-semiconductor (CMOS) neuron circuits. By systematically analyzing the energy-band structure, diode parameters, and dominant conduction mechanisms, the physical origin of the intrinsic thresholding behavior in the PN heterojunction neuron is identified. As a hardware neuron device, the PN heterojunction neuron exhibits rectification and nonlinear activation characteristics, while the threshold voltage (V_th) is 2.49 V and the rectification ratio (RR, ratio of current at ±3 V) is 10⁴, allowing the direct implementation of the rectified linear unit (ReLU) function at the device level. The PN heterojunction neuron reliably receives and processes summed currents from synapse devices, demonstrating accurate ReLU operation, where linear signal transmission occurs only when the total synaptic conductance (G_tot) exceeds 110 nS, while no signal is transmitted below 110 nS. Furthermore, by integrating the PN heterojunction neuron with a commercial transistor, signal propagation across multiple layers is attained, confirming compatibility with multilayer HDNNs. Owing to its simple structure, intrinsic nonlinearity, and high scalability, the PN heterojunction neuron provides an effective solution to the area and complexity challenges of CMOS-based neuron implementations and exhibits strong potential for highly integrated and energy-efficient HDNNs.

To overcome the bottleneck inherent in the von Neumann architecture and advance hardware-oriented neural network design, this study conceptually proposes a monolithic three-dimensional, vertically integrated neural network architecture that supports vertical multiply-accumulate operations and horizontal interlayer data transmission. As a core component of this proposed structure, we experimentally demonstrate an ion-based switching neuron device that exhibits rectified linear unit-type output characteristics depending on the total synaptic conductance. The proposed neuron device is designed to be highly compatible with synaptic devices operating across a wide range of conductance levels by incorporating a resistance element. Owing to its compact structure and suitability for monolithic 3D stacking, the proposed neuron enables significant projected reductions in area (≥10³-fold) and energy consumption (≥10⁵-fold) compared with conventional circuit-based neural networks. These results establish a device-level hardware basis and propose a scalable architectural direction toward high-density, energy-efficient, parallel in-memory computing systems.

While in-memory computing offers a promising approach to overcoming the limitations of the traditional von Neumann architecture, implementing an activation function, a critical component of neural networks, still requires substantial energy and area consumption when using conventional analog or digital circuitry. In this study, we introduce a two-terminal niobium-dioxide-based Peierls transition neuron (Peierls-neuron) that enables direct device-level implementation of the activation function. Through monolithic three-dimensional(3D) vertical integration of Peierls-neurons with synaptic devices, a highly compact neural network architecture is achieved featuring minimal interconnect overhead and maximum array density. A simple tuning method using a parallel resistor allows seamless compatibility with a broad range of synaptic conductance levels, thereby eliminating the need for additional peripheral circuits. Our integrated architecture achieves over 10⁴ times area reduction and up to 183.7 times energy savings compared with conventional activation function circuits. These results demonstrate a highly scalable and energy-efficient solution for the hardware implementation of neural network.

To implement a neuromorphic computing system capable of efficiently processing vast amounts of unstructured data, a significant number of synapse and neuron devices are needed, resulting in increased area demands. Therefore, we developed a nanoscale vertically structured synapse device that supports high-density integration. To realize this synapse device, the interface effects between the resistive switching layer and the electrode were investigated and utilized. Electrical and physical analyses were conducted to comprehend the operational mechanism of the developed synapse device. The results indicate that oxygen ions from the resistive switching layer were absorbed by the electrode, forming metal–oxygen bonds. The V O concentration in the switching layer that can change the total conductance of the device. To assess its potential as a synapse device in the neuromorphic system, the developed device was evaluated through pattern recognition simulation.

To achieve both excellent analog switching for training and retention for inference simultaneously, we investigated elevated-temperature (ET) training of Pr_0.7Ca_0.3MnO_3−x (PCMO) electrochemical random access memory (ECRAM).

The engineering filament evolution of HfO2-based resistive random access memory (RRAM) has shown promising advancements in analog synaptic weight updates during the training stage for neuromorphic systems. However, the significance of incorporating an additional selector to eliminate sneak-path currents has often been neglected. Therefore, this study addresses this issue by demonstrating linearly and symmetrically tuned synaptic weights in selector-less HfO2-based RRAM. By introducing an extremely thin Al2O3 layer in the HfO2 RRAM, we observed a nonlinear current–voltage behavior that effectively suppresses low-resistance states in the low-voltage regime, which act as sneak-path currents. Through simple numerical fitting, we determined that the Al2O3 layer functions as a built-in exponential resistor, and we investigated the impact of its thickness on the switching behavior. To further understand the role of the Al2O3 layer, we analyzed the set-switching mechanism of the selector-less RRAM by examining the real-time transient current response. Unlike an abrupt current jump typically observed in conventional RRAMs, we observed a sequential transition in the selector-less RRAM. This implies that conduction in the selector-less RRAM is in two steps through each oxide of the Al2O3/HfO2 stack. Therefore, the utilization of the Al2O3 both enables analogously modulated current response through an identical pulse scheme for the selected cell and suppresses unwanted updates of half-selected cells. The improved linearity of synaptic weight updates in the selector-less Al2O3/HfO2 RRAM allows for high pattern recognition accuracy on the MNIST dataset, based on the backpropagation algorithm performed in IBM AIHWKIT simulations.

Despite holding valuable information, unstructured data pose challenges for efficient recognition due to the difficulties in feature extraction using traditional Von-Neumann architecture systems, which are limited by power and time bottlenecks. Although biological neural signals offer crucial insights, they require more effective recognition solutions due to inherent noise and the vast volumes of data. Inspired by the human brain, neuromorphic systems have emerged as promising alternatives because of their parallelism, low power consumption, and error tolerance. By leveraging deep neural networks (DNNs), these systems can recognize imprecise data through two key processes: learning (feature extraction) and testing (feature matching and recognition). During the learning phase, DNNs extract and store unique features such as weight changes in synapse units. In the testing phase, new data are compared with the stored features for recognition. The parallelization of the neuromorphic system enables the efficient processing of large, imprecise datasets with minimal energy consumption. Nevertheless, the hardware implementation is essential for determining the full potential of DNNs. This paper focuses on synapse devices, which are the core units for hardware DNN implementations, and presents a biomedical application example: a rat neural signal recognition system implemented using a synapse device-based neuromorphic system.

A synaptic device with a multilayer structure is proposed to reduce the operating power of neuromorphic computing systems while maintaining a high-density integration. A simple metal–insulator–metal (MIM)-structured multilayer synaptic device is developed using an 8-inch wafer-based and complementary metal–oxide–semiconductor (CMOS) fabrication process. The three types of MIM-structured synaptic devices are compared to assess their effects on reducing the operating power. The obtained results exhibited low-power operation owing to the inserted layers acting as an internal resistor. The modulated operational conductance level and simple MIM structure demonstrate the feasibility of implementing both low-power operation and high-density integration in multilayer synaptic devices.