Ewout Martens

We present a 7-bit wireline digital-to-analog converter (DAC), fabricated in 5-nm FinFET CMOS. The number of source-series terminated (SST) cells in the output stage is reduced to 34 by employing cells with relative weight 1 and 4. Each differential cell integrates two single-ended three-stage 8:1 return-to-zero (RZ) multiplexers with an integrated SST driver and a clock pulse generator (CPG), which generates the required clock pulses for the multiplexers from an eight-phase clocking scheme. The clock buffers driving these cells feature shunt inductors to reduce power consumption and jitter. At 150 GSa/s, the effective number of bits (ENOB) was measured to be 4.1 b for a 72.8-GHz sinewave. The DAC consumes 621 mW from a 0.9- and 0.96-V supply. Eye diagrams of 150-GBd NRZ, PAM-4, and PAM-6 are demonstrated, pre-equalized using a 10-tap feedforward equalizer.

The recent proliferation of artificial intelligence and machine learning applications relying on large language models is fueling unprecedented demand for compute capacity. Associated with this is a need to scale capacities of short-reach optical transceivers towards multiplex Terabit/s, while maintaining integration density (frontpanel or beachfront density) and energy efficiency (pJ/bit). One option to scale transceiver capacity is to increase the bandwidth per lane from today's 200G to 400G or even higher: coherent transceiver technology is then expected to play an ever more important role. Photonics and electronics with higher bandwidths beyond 100GHz will play a crucial role. Integration of thin-film LiNbO3 modulator onto a Silicon Photonics platform is shown to be a viable option to meet the needs for new generations of optical transceivers. Front-end electronics such as linear modulator drivers and transimpedance amplifiers can rely on traveling-wave design approaches to allow continued bandwidth scaling despite (relative) slowing transistor speeds. Novel wireline data converter architectures can be used to overcome limitations of existing implementations. Maintaining signal integrity from photonics and electronics can be facilitated using both 2.5D and 3D integration approaches. While the introduction of novel materials and architectures will require time to further mature, optical transceivers operating at baudrates up to and beyond 200Gbaud are now just beyond the horizon.

This work presents a 2x Time-Interleaved (TI) Delta Sigma Modulator (DSM) Analog-to-Digital Converter (ADC) leveraging a 6b Noise-Coupled (NC) Noise-Shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset pre-sampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67dB/72dB SNDR/SNR over a 70MHz bandwidth while consuming 32mW.

A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations is presented. The ADC includes an input buffer where its distortion is tackled by calibration. A low-cost auxiliary channel is introduced that serves as a reference for the calibration. It employs only a quarter of the input swing of the main channel, thus achieving adequate linearity. The auxiliary channel is further utilized for the gain calibration, where a split-ADC-like calibration is proposed to ease residue amplifier design constraint. The coefficients in the digital post-distortion filter are iterated through a multi-step multi-layer LMS algorithm, which converges faster and is more robust than its single-step counterpart. The buffered ADC works under a 1 V power supply thanks to the calibration, consuming 19.2 mW, where the input buffer contributes 18% of the total power. The calibration improves the SFDR by $>$ 14 dB within the 1st Nyquist zone, and $>$ 8dB up to 4th Nyquist input zone. The design achieves 59.3 dB SNDR and 67.1 dB SFDR at Nyquist input. The entire calibration converges within $1\times 10$ $^{5}$ iterations.

This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.

This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm ² in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM).

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

A 4x interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a ``passive-hold'' mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A ``split-reference'' regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The ``scope-on-chip'' captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation.