Dmitri E. Nikonov

R. Ramesh(*rr73@rice.edu) R. Ramesh(*rr73@rice.edu)

As CMOS technologies face challenges in dimensional and voltage scaling, the demand for novel logic devices has never been greater, with spin-based devices offering scaling potential, at the cost of significantly high switching energies. Alternatively, magnetoelectric materials are predicted to enable low-power magnetization control, a solution with limited device-level results. Here, we demonstrate voltage-based magnetization switching and reading in nanodevices at room temperature, enabled by exchange coupling between multiferroic BiFeO₃ and ferromagnetic CoFe, for writing, and spin-to-charge current conversion between CoFe and Pt, for reading. We show that, upon the electrical switching of the BiFeO₃, the magnetization of the CoFe can be reversed, giving rise to different voltage outputs. Through additional microscopy techniques, magnetization reversal is linked with the polarization state and antiferromagnetic cycloid propagation direction in the BiFeO₃. This study constitutes the building block for magnetoelectric spin-orbit logic, opening a new avenue for low-power beyond-CMOS technologies.

Devices based on the spin as the fundamental computing unit provide a promising beyond-complementary metal-oxide-semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. One such option is a Magneto-Electric Spin-Orbit (MESO) device, an attojoule-class emerging technology promising to extend Moore’s law. This paper presents circuit design and optimization techniques such as device stacking and a canary circuit-based asynchronous clock pulse generation scheme for Magneto-Electric Spin-Orbit (MESO) device technology. With these targeted circuit techniques, the MESO energy efficiency can be improved by ~1.5x. Novel architectures for arithmetic logic and effective realization of in-memory computing are also proposed that utilize the unique properties of this promising new technology.

A prominent approach to solving combinatorial optimization problems on parallel hardware is Ising machines, i.e., hardware implementations of networks of interacting binary spin variables. Most Ising machines leverage second-order interactions although important classes of optimization problems, such as satisfiability problems, map more seamlessly to Ising networks with higher-order interactions. Here, we demonstrate that higher-order Ising machines can solve satisfiability problems more resource-efficiently in terms of the number of spin variables and their connections when compared to traditional second-order Ising machines. Further, our results show on a benchmark dataset of Boolean k-satisfiability problems that higher-order Ising machines implemented with coupled oscillators rapidly find solutions that are better than second-order Ising machines, thus, improving the current state-of-the-art for Ising machines.

While the scaling of CMOS electronics continues and reaches the sub-10 nanometer range, active research is being conducted on logic devices beyond CMOS to find a path to a more energy efficient integrated circuit platform for computing. Among them, a prominent option is spintronic devices, remarkable for their non-volatility and low switching energy. Simulation is the key part of this research due to spintronics’ reliance on novel materials, device structures, and circuit architecture. We review recent publications which often traverse these hierarchical levels of the computing stack. Prevalent methods, comparison with experiments, use in proposing new logic concepts are surveyed.

A generalized and fast multidomain phase-field-based compact model for the metal-ferroelectric-metal (MFM) capacitor is presented. Time-dependent Landau–Ginzburg (TDGL) and Poisson’s equations are solved self-consistently to model the polarization dynamics. Additionally, physics-based empirical relationships for voltage-dependent kinetic and gradient energy coefficients are formulated. It is also demonstrated how gradient energy coefficient needs to be modified to accurately capture the physics of the device when a coarse simulation grid is used for fast computation. The developed model is 30 000 times faster than our prior multidomain phase-field model with no degradation in accuracy. Moreover, a further computational speedup has been achieved by decreasing the number of Poisson solver nodes with a slight compromise of accuracy. The model shows a good agreement with the experimental results of both transient characteristics and minor hysteresis loops. The proposed model has the potential to facilitate fast and accurate simulations of large-scale circuits containing ferroelectric capacitors.

Combinatorial optimization problems (COP) are ubiquitous and practical in our daily life, but many of them are NP-hard and intractable to solve using conventional computing. Ising model-based annealer has gained increasing attention due to its efficiency in finding fast and approximate solutions. However, such solvers are suffering from scalability problem due to quadratically increasing spins, and there are few hardware designs proposed to support large-scale COPs. In this paper, we propose scalable in-memory annealers to solve the large-scale travelling salesman problem (TSP) with crossbar arrays of FinFET based charge trap transistors. The intrinsic temporal noise of the drain current caused by trapping/detrapping is used to realize the annealing process. We apply two kinds of hardware implementations to map Ising model: 1) Hopfield neural network (HNN) based design, converting from a graph network to a regular neural network to utilize crossbar memory arrays; 2) index-based design, using index to record the order to avoid the quadratic scaling up of spins to represent all permutations. For both implementations, hierarchical clustering algorithms are adopted to enable the solving of large-scale TSP and overcome the scalability challenge. We further speed up the system convergence by updating non-adjacent clusters in parallel with equal size k-means clustering. At last, three hardware designs (HNN with conventional and equal-size clustering, index method with conventional clustering) are tested with up to 1060-city problems and benchmarked by the system-level simulation to show their trade-offs. They all show benefits on fast convergence and ultra-low energy compared with state-of-the-art annealers, and present advantages on accuracy, chip area, or latency/energy consumption, respectively.

As is well known, the traditional electronics as well as exploratory logic and memory devices have relied on mono- or bi-elemental semiconductors for many decades. Oxides served an indispensable, but still secondary role of capacitor dielectrics, insulation, tunneling barriers, and so on. The functionality of oxides putting them at the center stage of computing (such as conduction, ferroelectricity, magnetic/spin, piezoelectric, ion drift, metal–insulator transitions, etc.) was researched from the material science side throughout this time. However, the work on realistic computing devices based on these properties really took off in the past decade. Oxides allow for a wider variety of phenomena which can be utilized (multiferroic materials, spin waves, to name a few). They require more sophisticated theoretical treatment (such as indirect exchange, Dzyaloshinskii–Moriya interaction, and topological materials) than traditional semi-conductors. In some cases, the single crystal state and close to atomically flat interfaces require novel fabrication methods. All these provide exciting opportunities to advance computing.

Single crystals of BaTiO₃ exhibit small switching fields and energies, but thin-film performance is considerably worse, thus precluding their use in next-generation devices. Here, we demonstrate high-quality BaTiO₃ thin films with nearly bulk-like properties. Thickness scaling provides access to the coercive voltages (−1) required for future applications and results in a switching energy of −3 (corresponding to 3 device). While reduction in film thickness reduces coercive voltage, it does so at the expense of remanent polarization. Depolarization fields impact polar state stability in thicker films but fortunately suppress the coercive field, thus driving a deviation from Janovec–Kay–Dunn scaling and enabling a constant coercive field for films 3 thin films onto silicon substrates is shown. We also discuss what remains to be demonstrated to enable the use of these materials for next-generation devices.