Amritakar Mandal

Summary: The paper presents performance analysis of least‐mean‐square algorithm based adaptive filter embedded with constant false alarm rate (CFAR) detector for the purpose of better detection of target under non‐homogeneous clutter environment in radar application. The objective of this paper is to develop a method by redesigning the radar detector in such a way to emphasize the target response and de‐emphasize the clutter response. The hardware implementation using pipeline technique for the adaptive filter reveals its capability to support high sampling frequency, which is an ardent necessity for high performance radar. The moderate area‐delay‐product and low power consumption have made it suitable for hardware realization for such application. The extensive MATLAB simulation of proposed design shows remarkable improvement of detection performance in terms of signal‐to‐noise ratio of 17 dB considering probability of detection at 0.8 over the generic cell averaging CFAR (CA‐CFAR). Copyright © 2015 John Wiley & Sons, Ltd.

The recent years have seen an unprecedented increase in the demand for superior performance of radar signal processor. The main challenge in a radar system is to maintain the probability of a false alarm rate constant even under an uncertain time-varying clutter environment. The objective of this paper is to develop a method for enhanced clutter/interference suppression by redesigning the radar detector in such a way to emphasize the target response and de-emphasize the clutter response. To achieve this, we have proposed a hardware architecture that implements least mean square algorithm-based adaptive filter along with a constant false alarm rate (CFAR) technique for the purpose of better detection of target under a non-homogeneous clutter environment. An adaptive design of the CFAR-filter technique has been used to improve probability of detection by increasing signal-to-noise ratio. The efficacy of the proposed architecture is corroborated with MATLAB simulations and hardware synthesis.

Adaptive equalizer is an indispensable component for high-speed reliable data transmission through wired as well as wireless time-dispersed communication channels to minimize Inter Symbol Interference (ISI). The non-linear Adaptive Decision Feedback Equalizer (ADFE) finds enormous use in applications where the channel distortion is severe for a linear equalizer to handle. High hardware cost of the system makes an urge to redesign it in order to minimize overall circuit complexity and cost. In this paper, ADFE based on pipelined CORDIC architecture is presented using LMS algorithms. The realization results more power efficient, better speed and throughput with good convergence.

The differences in drain current and drain voltage characteristics of top gate and bottom gate Organic Thin Film Transistor (OTFT) structures are analyzed by two dimensional numerical device simulators. Further discussion shows different characteristics parameters of OTFTs. Transistor based on organic semiconductor (conjugated or conducting polymers) as active layer to manage electric current flow is known as OTFTs. The performance parameters of OTFTs are evaluated from output and transfer characteristics of different structures of OTFTs. Device characteristics parameters have been evaluated in terms of drain current, mobility, on/off current ratio, threshold voltage, subthreshold slope and transconductance. OTFTs are considered as promising device for future development of their various applications in the areas of low-cost and large-area electronics. Further this paper thoroughly discusses the overall performance and applications of OTFTs in various fields.

Digital Signal Processing (DSP) systems involve a wide spectrum of DSP algorithms and their realizations are often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. This paper presents the design of Adaptive Finite Impulse Response (FIR) filter for moving target detection in various clutter conditions in Radar Receiver. The design uses pipelined COordinate Rotation DIgital Computer (CORDIC) unit and pipelined multiplier to get high system throughput and reduced latency in each of the pipelined stage. Saving area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed design can be achieved through optimization in the number of micro rotations. For better adaptation and performance of Adaptive Filters and to minimize quantization error, the numbers of iterations are also optimized.