Yong Wang

Current security solutions predominantly rely on cloud-based implementations, often neglecting computational resource constraints and operational efficiency. While contemporary methodologies typically require additional training, the few that operate without retraining frequently yield suboptimal performance. To address these limitations, this work leverages a pre-trained MTCNN architecture to detect faces of copyright-protected individuals. We construct a facial landmark database comprising five critical fiducial points, which serves as a supplementary module integrated into the stable diffusion framework, enabling real-time security filtering for synthesized video content. The proposed system utilizes MTCNN models pre-trained in the cloud to build a repository of copyrighted facial signatures, generating a geometric parameter database of facial landmarks. This database, coupled with a parallel verification unit, functions as a plugin within the standard Stable Diffusion pipeline. By leveraging Stable Diffusion’s native decoder, we decode stochastic frames from the U-Net latent representations and perform real-time comparative analysis to identify potential copyright violations in generated video sequences. Upon detecting an infringement, an on-screen display (OSD) alert notifies the user and immediately halts the text-to-video (T2V) generation process. Experimental evaluations demonstrate that our framework effectively mitigates the resource constraints and latency issues inherent in edge deployment scenarios of prior security implementations. Leveraging MTCNN’s proven robustness and extensive edge compatibility for facial recognition, the proposed detection and obfuscation plugin integrates seamlessly with Stable Diffusion while preserving generation quality.

Motor imagery-brain-computer interfaces (MI-BCIs) have demonstrated significant potential for neurorehabilitation and cognitive neuroscience. However, a standardized and reproducible MI-EEG workflow for configurable spatial-temporal-frequency feature analysis remains limited, and many pipelines require complex configuration and parameter tuning with limited interpretability, hindering practical deployment and generalization. To address these challenges, an STFEEG-Tool was developed to provide a user-friendly, standardized, and interpretable workflow for EEG decoding in MI paradigms. STFEEG-Tool enables fine-grained configuration of temporal, frequency-band, and spatial segmentation, allowing the extraction of multiscale MI features. The toolbox integrates multiple feature extraction algorithms, including common spatial patterns (CSP) and divergence-based CSP (div-CSP), along with various classifiers, such as support vector machines (SVMs), Ridge Regression Classifier, and Lasso Classifier. A dynamic time-frequency scalp topographical map is provided to summarize spatial patterns across time-frequency segments and support interpretation of decoding results. Overall, STFEEG-Tool serves as a reproducible and extensible platform for fine-grained MI-EEG analysis, facilitating the translation of fine-grained decoding pipelines into practical, user-oriented applications.

Motor imagery-brain-computer interfaces (MI-BCIs) have demonstrated significant potential for neurorehabilitation and cognitive neuroscience. However, a standardized and reproducible MI-EEG workflow for configurable spatial-temporal-frequency feature analysis remains limited, and many pipelines require complex configuration and parameter tuning with limited interpretability, hindering practical deployment and generalization. To address these challenges, an STFEEG-Tool was developed to provide a user-friendly, standardized, and interpretable workflow for EEG decoding in MI paradigms. STFEEG-Tool enables fine-grained configuration of temporal, frequency-band, and spatial segmentation, allowing the extraction of multiscale MI features. The toolbox integrates multiple feature extraction algorithms, including common spatial patterns (CSP) and divergence-based CSP (div-CSP), along with various classifiers, such as support vector machines (SVMs), Ridge Regression Classifier, and Lasso Classifier. A dynamic time-frequency scalp topographical map is provided to summarize spatial patterns across time-frequency segments and support interpretation of decoding results. Overall, STFEEG-Tool serves as a reproducible and extensible platform for fine-grained MI-EEG analysis, facilitating the translation of fine-grained decoding pipelines into practical, user-oriented applications.

In ECG classification applications, binarized convolutional neural networks (bCNNs) show great potential to achieve extremely low power consumption through 1-bit quantization. Existing bCNN approaches typically extract spatial features from the full ECG image without leveraging its sparsity, thereby introducing unnecessary computations and hardware resources. Meanwhile, inter-patient variability of ECG features degrades the classification performance due to accuracy loss caused by the binarization operation. To address these challenges, this paper proposes an energy-efficient ECG classifier based on a bCNN with on-chip learning. A patch-by-patch computation approach is used to reduce both power consumption and memory usage. Instead of processing the entire image, the ECG image is divided into small patches, and only the patches containing valid data are involved in feature extraction. An on-chip learning method is employed to improve classification accuracy among patients by updating the model weights using both the acquired bCNN features and the R-peak interval data. In addition, a reconfigurable convolutional processing element array and a base-2 softmax structure are designed to further reduce the hardware resources. The proposed classifier is verified on an FPGA, achieving a classification accuracy of 97.55% and a specificity of 89.15%. Synthesized using a 55 nm CMOS process, the ECG classifier occupies an area of 0.43 mm${}^{2}$. With a supply voltage of 1.2 V, the classifier consumes an average energy of 0.12 $\mu$J per classification and 0.09 $\mu$J per on-chip learning, making it suitable for wearable ECG classification application.

Binarized convolutional neural networks (bCNNs) are favored for the design of low-storage, low-power cardiac arrhythmia classifiers owing to their high weight compression rate. However, multi-class classification of ECG signals based on bCNNs is challenging due to the accuracy loss introduced by the binarization operation. In this paper, an effective multi-classifier system is proposed for electrocardiogram (ECG) signals using a binarized depthwise separable convolutional neural network (bDSCNN) with the merged convolution–pooling (MCP) method. The binarized depthwise separable convolution layer is adopted to reduce the increased number of parameters in multi-classification systems. Instead of operating convolution and pooling sequentially as in a traditional convolutional neural network (CNN), the MCP method merges pooling together with convolution layers to reduce the number of computations. To further reduce hardware resources, this work employs blockwise incremental calculation to eliminate redundant storage with computations. In addition, the R peak interval data are integrated with P-QRS-T features to improve the classification accuracy. The proposed bDSCNN model is evaluated on an Intel DE1-SoC field-programmable gate array (FPGA), and the experimental results demonstrate that the proposed system achieves a five-class classification accuracy of 96.61% and a macro-F1 score of 89.08%, along with a dynamic power dissipation of 20 μW for five-category ECG signal classification. The hardware resource usage of BRAM and LUTs plus REGs is reduced by at least 2.94 and 1.74 times, respectively, compared with existing ECG classifiers using bCNN methods.

This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected to improve the calibration effects as well as the SNR, for the SAR ADC. Measurement results show, upon the proposed calibration, the SAR’s INL and SNR are improved by 3[ ]LSB and 9[ ]dB, respectively, compared to when the noise shaping is off. Fabricated using a 55[ ]nm CMOS MOMCAP technology and tested with a −2.5[ ]dB sinewave input, the bridged SAR ADC achieves an SNR of 62.2[ ]dB and an INL better than 1[ ]LSB, when consuming a power of [ ], at a supply voltage of 1.2[ ]V and sampling frequency of 50[ ]kHz. The ADC’s active area is [ ].