Andreas Burg

Next-generation channel coding has stringent demands on throughput, energy consumption, and error rate performance while maintaining key features of 5G New Radio (NR) standard codes such as rate compatibility, which is a significant challenge. Due to excellent capacity-achieving performance, spatially-coupled low-density parity-check (SC-LDPC) codes are considered a promising candidate for next-generation channel coding. In this paper, we propose an SC-LDPC code family called edge-spreading Raptor-like (ESRL) codes. Unlike other SC-LDPC codes that adopt the structure of existing rate-compatible LDPC block codes before coupling, ESRL codes maximize the possible locations of edge placement and focus on constructing an optimal coupled matrix. Moreover, a new graph representation called the unified graph is introduced. This graph offers a global perspective on ESRL codes and identifies the optimal edge reallocation to optimize the spreading strategy. We conduct comprehensive comparisons of ESRL codes and 5G-NR LDPC codes. Simulation results demonstrate that when all decoding parameters and complexity are the same, ESRL codes have obvious advantages in error rate performance and throughput compared to 5G-NR LDPC codes in some specific scenarios (low and high number of iterations), making them a promising solution towards next-generation channel coding.

This paper introduces a novel method for device-free human detection by leveraging existing wireless communication signals from 4G-long-term evolution (4G-LTE) systems. By utilizing the pervasive 4G-LTE signals, our approach enhances the efficiency and coverage of human presence detection compared to WiFi signal based approaches. A previously overlooked, but crucial human presence scenario involving subtle human activities is successfully addressed and detected. Effective human presence detection relies heavily on precise feature extraction from channel estimates and careful feature selection. Through a detailed analysis and comparison of features discussed in previous work, along with the introduction of new features, we develop a machine learning-based approach to identify the most effective features for detecting human presence. Our machine learning model, trained with these selected features, is tested across different buildings and various scenarios using a commercial 4G-LTE network. The results demonstrate that our selected features significantly enhance detection accuracy and robustness, outperforming features introduced in previous literature across diverse environments.

Belief propagation (BP) decoding has been recognized for its capacity-approaching performance and high throughput when decoding long low-density parity-check (LDPC) codes. However, the application of BP decoding for short codes is hindered by dense parity-check matrices (PCMs) and prevalent short cycles in the Tanner graph. In this paper, we introduce a general method to extract an optimized sparse PCM for short binary block codes, which removes length-four cycles and enhances the connectivity of short cycles to enable BP decoding with improved performance. Notably, for short binary codes with lengths up to 64, our BP decoding performance approaches the maximum likelihood bound and surpasses the best-reported BP results with reduced computational complexity. Compared with other universal decoding algorithms, BP decoding using our extracted sparse PCMs is competitive in terms of both error-rate performance and computational complexity. These promising results suggest that our method to improve BP decoding for short codes is a step toward a practical universal BP decoder for next-generation communication systems.

We propose an iterative logistic weight based decoder for open forward error correction (oFEC) codes. Compared to Chase-Pyndiah decoding with 93 error patterns, our decoder achieves similar performance with lower complexity.

Gain-cell embedded dynamic random access memory (GC-eDRAM) has emerged as a suitable choice for embedded memory implementation due to its high density, low leakage current, and voltage scaling compatibility. This work presents a 16-kB 3T-1C GC-eDRAM macro, featuring an innovative internal reference voltage generation mechanism and an on-chip dc–dc converter for internal boosted supply generation. The memory architecture is partitioned to efficiently accommodate the reference generation and implement a variation-tolerant sensing scheme. The on-chip dc–dc converter is employed for internally generating a boosted voltage that enhances charge retention to increase the data retention time (DRT). The memory macro was implemented in a 65-nm CMOS technology and fabricated as part of a research test chip. Measurements across a spectrum of boosted voltages and different temperature points, show a significant improvement in DRT compared with similar GC-eDRAM designs, without compromising area, performance, or power dissipation.

Node-based successive cancellation list (SCL) decoding has received considerable attention in wireless communications for its significant reduction in decoding latency, particularly with 5G New Radio (NR) polar codes. However, the existing node-based SCL decoders are constrained by sequential processing, leading to complicated and data-dependent computational units that introduce unavoidable stalls, reducing hardware efficiency. In this paper, we present a frame-interleaving hardware architecture for a generalized node-based SCL decoder. By efficiently reusing otherwise idle computational units, two independent frames can be decoded simultaneously, resulting in a significant throughput gain. Based on this new architecture, we further exploit graph ensembles to diversify the decoding space, thus enhancing the error-correcting performance with a limited list size. Two dynamic strategies are proposed to eliminate the residual stalls in the decoding schedule, which eventually results in nearly $2\times$ throughput compared to the state-of-the-art baseline node-based SCL decoder. To impart the decoder rate flexibility, we develop a novel online instruction generator to identify the generalized nodes and produce instructions on-the-fly. The corresponding $28$ nm FD-SOI ASIC SCL decoder with a list size of $8$ has a core area of $1.28$ mm $^2$ and operates at $692$ MHz. It is compatible with all 5G NR polar codes and achieves a throughput of $3.34$ Gbps and an area efficiency of $2.62$ Gbps/mm $^2$ for uplink $(1024,512)$ codes, which is $1.41\times$ and $1.69\times$ better than the state-of-the-art node-based SCL decoders.

Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3 dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR blocklengths and code rates, which is a significant challenge. In this paper, we present a high-performance and low-complexity LDPC decoder, tailor-made to fulfill the 5G requirements. First, to close the gap between belief propagation (BP) decoding and its approximations in hardware, we propose an extension of adjusted min-sum decoding, called generalized adjusted min-sum (GA-MS) decoding. This decoding algorithm flexibly truncates the incoming messages at the check node level and carefully approximates the non-linear functions of BP decoding to balance the error-rate and hardware complexity. Numerical results demonstrate that the proposed fixed-point GA-MS has only a minor gap of 0.1 dB compared to floating-point BP under various scenarios of 5G standard specifications. Secondly, we present a fully reconfigurable 5G NR LDPC decoder implementation based on GA-MS decoding. Given that memory occupies a substantial portion of the decoder area, we adopt multiple data compression and approximation techniques to reduce 42.2% of the memory overhead. The corresponding 28nm FD-SOI ASIC decoder has a core area of 1.823 mm $^{2}$ and operates at 895 MHz. It is compatible with all 5G NR LDPC codes and achieves a peak throughput of 24.42 Gbps and a maximum area efficiency of 13.40 Gbps/mm $^{2}$ at 4 decoding iterations.