Carsten Wulff

This article presents a frequency quadrupler with 32% fractional bandwidth (66-92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multi-port driven push-push complementary architecture for the first stage to generate differential signals for the second doubler with high fundamental harmonic rejection. The second doubler based on the NMOS-based push-push architecture uses gain enhancement to achieve a maximum conversion gain of -4 dB for the quadrupler. The quadrupler with an output saturation power (Psat) of -2.6 dBm achieves first-to third-harmonic rejections of more than 36 dBc across the 3-dB bandwidth. The compact quadrupler has a core area of 0.09 mm2, while consuming a DC power of 6.2 mW from a 0.8 V supply with an input power of 0 dBm at 20 GHz.

This article presents a D-band Low Noise Amplifier (LNA) for joint radar-communication applications in 22-nm CMOS technology. The 4-stage LNA uses transistor switching and bias class changes to achieve dual-mode functionality. In the radar mode, the LNA achieves gain of 17 dB, Noise Figure (NF) of 7.7 dB, 3-dB bandwidth (BW) of 117-129 GHz, and IP1dB of -20 dBm respectively. In the communication mode, the LNA achieves gain of 22.6 dB, NF of 8.5 dB, BW of 115.9-128.9 GHz, and IP1dB of -29 dBm respectively. The power consumption for the radar and communication modes are 13 mW and 12.2 mW respectively. The LNA has a core area of 0.06 mm2.

In this paper, behavioural circuit simulations are used to compare the leapfrog control-bounded analog-to-digital converter to relevant continuous-time sigma-delta modulators in terms of nominal performance and sensitivity to component variations, clock jitter and finite gain-bandwidth product. Simulations show that the nominal performance of the leapfrog is similar to that of a continuous-time sigma-delta modulator of the same loop filter order and with the same number of quantization levels. Component variations in the leapfrog's analog system will introduce errors in the final output, unless the coefficients of the reconstruction filter are modified accordingly. Nevertheless, the simple, modular structure, analytical stability guarantee and single-bit quantizers make the leapfrog an interesting alternative to conventional continuous-time sigma-delta modulators.

This paper ^{1 1} This work has been supported by the Centre for Innovative Ultrasound Solutions (CIUS), a Norwegian Research Council appointed Centre for Research Based Innovation. Research Council of Norway grant number 237887. presents a noise-shaping SAR ADC with an on-chip, foreground capacitive DAC (CDAC) calibration system. At start-up, the ADC uses the LSBs in the CDAC to measure and digitize the errors of the MSBs. A synthesized digital module accumulates the noise-shaped measurements, computes calibration coefficients, and corrects ADC codes at run-time. The loop filter implements two optimal zeros and two poles, and achieves 27.8 dB in-band attenuation at an oversampling rate (OSR) of 4. The prototype is implemented in 28 nm FDSOI, and achieves 68.2 dB SNDR at 5 MHz bandwidth, while consuming 108.7 μW from a 0.8 V supply. The Walden FOM is 5.2 fJ/conv.-step. The layout of the ADC is compiled from a netlist, a rule file, and an object definition file.

This paper presents a low-power 9-bit compiled successive-approximation register (SAR) analog-to-digital converter (ADC) for Bluetooth low energy receivers. The ADC is compiled from a SPICE netlist, a technology rule file, and an object definition file into a design rule check and layout versus schematic clean layout and schematic in 28-nm FDSOI. The compiled SAR ADC reduces the design time necessary to port to a new technology, and to demonstrate technology porting the same SAR ADC architecture is compiled in 28-nm FDSOI with Input/Output (IO) transistors. This paper also includes a comparator clock generation loop that uses the bottom plate of the capacitive digital-to-analog converter. The proposed compiled core transistor SAR ADC achieves the state-of-the-art Figure of Merit (FoM) of 2.7 fJ/conv.step at 2 MS/s, and 3.5 fJ/conv.step at 20 MS/s with an area of 0.00312 mm ² .

A low power 9-bit compiled SAR ADC is presented. The ADC is compiled from a netlist, rule file, and object definition file into a DRC/LVS clean layout and schematic in 28nm FDSOI. The presented ADC also includes a comparator clock generation loop that use the bottom plate of the CDAC. The proposed compiled ADC achieves a FoM of 2.7fJ/conv.step at 2MS/s, and 3.5fJ/conv.step at 20MS/s with an area of 0.00312mm². To demonstrate process independence the same SAR architecture is compiled in 28nm FDSOI with IO transistors.

Oversampling and noise-shaping have in recent years been introduced to SAR ADCs to improve the conversion accuracy. Similar to delta-sigma ADCs, this is done by means of a feedback loop containing a loop filter. In this paper, the high-level design of this loop filter is discussed, and important differences to classical delta-sigma loop filter design are pointed out. Among others, it is found that the poles of the noise transfer function, and not only the zeros, play a significant role on the conversion accuracy. Based on this, a new loop filter topology with four poles and two zeros is proposed and compared to existing loop filters. This reveals that the proposed loop filter can yield more energy-efficient noise-shaping SAR ADCs than the ones seen in the literature today.

We present a differential comparator-based switched-capacitor (CBSC) pipelined ADC with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution 23 times. The ADC is manufactured in a 90 nm CMOS technology. The ADC core is 0.85 mm × 0.35 mm, with a 1.2 V supply for the core and 1.8 V for the input switches. The ADC has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.