Sivanantham Sathasivam

Introduction: This study presents a Field-Programmable Gate Array (FPGA)-based convolutional neural network (CNN) accelerator for preliminary Parkinson's disease (PD) handwriting classification using hand-drawn circle images, with emphasis on arithmetic-level optimization through efficient multiplier architectures. Although optimized multipliers have been extensively studied for machine learning acceleration, their application-specific effects on inference consistency and hardware efficiency in healthcare-oriented FPGA implementations remain underexplored. Methods: To address this issue, a lightweight binary CNN classifier, trained on Google Colab, is deployed on FPGA hardware and evaluated with three multiplier architectures: standard multipliers, approximate logarithmic multipliers, and Karatsuba multipliers. The desktop CNN model was evaluated using both non-augmentation validation and standard augmentation strategies. The primary evaluation methodology used a non-augmentation validation approach, in which augmentation was applied exclusively to the training set, resulting in a software validation accuracy of 92.86%. The standard augmentation strategy achieved a validation accuracy of 97.83% and was used to compare the effects of augmentation before splitting. The trained model was quantized to Q4.12 fixed-point precision and implemented on FPGA hardware, where dense-layer computations were performed using different multiplier architectures. Hardware inference was validated on the NewHandPD hand-drawn circle dataset, and FPGA outputs were compared with software inference results via graphical analysis and Mean Absolute Deviation (MAD) to assess numerical consistency. Results: Experimental results indicate that the FPGA-based implementation achieved classification behavior closely aligned with software inference while improving hardware efficiency. Under the non-augmentation validation approach, the FPGA implementation achieved 89.73% accuracy compared to 92.86% in software, whereas the standard augmentation strategy achieved 95.40% accuracy compared to 97.83% in software using the Approximate Logarithmic Multiplier. Discussion: The results indicate the potential feasibility of lightweight CNN deployment with optimized multipliers for resource-efficient edge healthcare applications. However, due to the limited dataset size, the presented findings should be interpreted as a preliminary proof-of-concept study rather than definitive clinical validation.

Small delay defects (SDD) based test escapes are caused by the nature of transition delay fault (TDF) ATPG, which propagates the fault effect along the shorter path in the interest of run time. However, owing to the benefits of a lesser pattern count and complexity, TDF ATPG is the most feasible option for delay testing. Faster than at-speed testing enhances the likelihood of detecting SDD. To generate the optimal test option and prevent over or under-testing the circuit, it is necessary to select the appropriate test clock period. The recently introducedWeighted slack percentage (WeSPer) metric is used in this article to identify the best SDD test option. The method’s benefit is combined with the proper selection of the optimal clock frequency to test the SDD. This article proposes an optimal test clock period selection method by considering the size of the smallest possible delay defect size that can fail the circuit during at-speed operation and the fault’s propagation delay. The proposed method is applied to the set of ISCAS89 and ITC99 benchmark circuits to evaluate its effectiveness.

This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, bridges, void formation, thermal and physical stress, etc., during the TSV fabrication and stacking of 3D ICs. The repair mechanism provides a redundancy feature to replace the failing TSVs with spare TSVs in the design. It provides a significant impact on yield compared to the standard TSV testing approach. Further analysis was performed on different stacked levels of 3D ICs, and the results were compared with the existing industrial methods in terms of the yield and test time parameters. The proposed mechanism showed a significant improvement of 12.5% in the yield and 17.5% in the test time and also recovered all defective chips efficiently.

Preserving the visual quality is a major constraint for any algorithm in image and video processing applications. AVC and HEVC are the extensively used video coding standards for various video processing applications in recent days. These coding standards use filters to preserve the visual quality of the processed video. To retain the quality of the reconstructed video, AVC uses an in-loop filter, called the deblocking filter, while HEVC uses two in-loop filters, the sampling adaptive offset filter and the deblocking filter. These filters are implemented in hardware by adopting various optimization techniques such as reduction of power utilization, reduction of algorithm complexity, and consuming lesser area. The quality of the reconstructed video should not be impacted by these optimization measures. For the HEVC/H.265 coding standard, a parallel edge deblocking filter architecture is designed, and the effectiveness of the parallel edge filter architecture is evaluated using various quantization values for various resolutions. The quality of the parallel edge filter architecture is on par with the HEVC reference model.

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

Compensating the error using additional circuitry is mandatory in a low-error fixed-width multiplier. Instead of compensating the error, reconfiguring n-bit fixed-width multiplier to n/2-bit error-free full-width multiplier using decomposed multiplication is proposed in this paper. The decomposed block multiplication using an area-efficient New Bit Pair Recoding (NBPR) algorithm in fixed-width mode shows a relatively lesser truncation error than existing truncated multipliers. Reconfigurable 16 x 16 NBPR multiplier in three different modes (8 x 8, 16 x 8, 16 x 16) with a fixed 16-bit product is verified on the TSMC 65nm CMOS standard cell library. The experimental results show that the NBPR multiplier consumes a lesser area than standard Booth multipliers. Evaluating the proposed multiplier in imaging shows improved PSNR with minimal error compared to other fixed-width multipliers.