Johan Bauwelinck

To meet the demand for low cost, size, weight, and power (C-SWAP) signal routing in the growing satellite and space markets, we propose and demonstrate an all-silicon fully integrated mmWave radio-over-fiber (RoF) transceiver front-end for frequency bands in the range of 18–36 GHz. The opto-electronic front-end consists of a radio frequency integrated circuit (RFIC) with both transmit and receive paths manufactured in a radiation-tolerant SiGe process, connected to the optical components contained on silicon photonic (SiPh) photonic integrated circuits (PICs). The RX uses a Ge PD, followed by a resonant photoreceiver and a resonant driver on the RFIC. The TX uses a resonant predriver and resonant driver on the RFIC, and an SiPh traveling-wave Mach–Zehnder modulator (TW-MZM) on the PIC. The RX and TX on the RFIC exhibit a total DC power consumption of 212 and 230 mW, respectively. The full-RoF-link is characterized through vector network analyzer (VNA) measurements, and its performance is verified through time-domain experiments at different carrier frequencies, resulting in 1-GBd 128-QAM with 5.2% EVM and 5-GBd 64-QAM with 9.1% EVM on a 22-GHz carrier, and 10-GBd 16-QAM/32-QAM with 11.2% EVM on a 28-GHz carrier.

This article presents a direct-drive optical transmitter (Tx) using common-cathode (CC) type single-mode (SM) 1060 nm vertical-cavity surface-emitting laser (VCSEL) suitable for medium-reach transmission (< 5 km) for linear pluggable optics (LPO)-based inter-cluster datacenter interconnect. The VCSELdriver featuring 4 channels is implemented in 28 nm bulk complementary metal-oxide semiconductor (CMOS) technology and co-designed with a GaAs-based 1060 nm VCSEL array. A VerilogA-based VCSEL device model with self-heating-induced voltage and optical power adjustments is introduced to facilitate co-design and (co-)optimization electro-optical interface. Two CMOS inverter-based equalizers, based on an active inductor and a T-coil, are used to enhance the driver bandwidth. A group-delay compensator is added to compensate the VCSEL group-delay variation and improve in-band gain flatness. The VCSEL features an optimal-3 dB BW of 31 GHz with 6 mA current bias. The optical Tx successfully demonstrated 60 Gbaud non-return-to-zero (NRZ) transmission with a SM 1060 nm VCSEL over 5 km single-mode fiber (SMF) using a 10-tap feed-forward-equalizer (FFE) with a record-high FEC-corrected bitrate-distance product of 283.47 Gb/s.km. For the electro optical transmission experiment, the optical Tx achieves a Tx energy-efficiency of 0.94 pJ/b with a 6 mA current biased VCSEL having-2.7 V supply at the CC terminal.

We present an O-band four-channel coarse wavelength-division-multiplexed (CWDM) receiver implemented on a silicon nitride (SiN) photonic integrated circuit (PIC) platform, enabled by micro-transfer printing of InGaAs/InP photodiodes. The PIC incorporates a cascaded Mach–Zehnder interferometer (MZI) lattice filter demultiplexer and four high-speed photodiodes. The demultiplexer achieves low insertion loss (1.7–2.4 dB) and crosstalk below -14 dB across the 1270–1330 nm grid. The printed photodiodes exhibit responsivities of 0.54–0.72 A/W across the four channels and a 33 GHz 3-dB bandwidth at 1310 nm under a −2 V bias. High-speed back-to-back reception of 32 Gbit/s non-return-to-zero (NRZ) signals is demonstrated on all channels, yielding open eye diagrams and bit-error rates (BERs) below 10 ⁻⁴ at demultiplexer-received optical powers above −11 dBm, obtained without a transimpedance amplifier. These results underscore the potential of micro-transfer printed InGaAs/InP photodiodes on SiN as a scalable solution for high-speed O-band receivers in short-reach interconnects and optical I/O.

We demonstrate the first co-integration of a wafer-scale single-layer graphene electro-absorption modulator (EAM) with a high-speed SiGe bipolar CMOS (BiCMOS) electronic integrated circuit (EIC), achieving robust operation up to 25 GBd. The scalable graphene EAM, fabricated in a 300 mm CMOS pilot line, exhibits an intrinsic electro-optic (EO) bandwidth of 11.2 GHz. To overcome the RC-limitation and simultaneously enable low-voltage operation, the EIC was co-designed with a 30 Ω internal termination impedance and amplifies the voltage swing by a factor of 3. This optimization increased the effective EO bandwidth and allowed the co-integrated system to produce open eye diagrams at 25 GBd from a low 500 mV p p input drive voltage. We report measured Q -factors and an estimated bit error rate of 1.37 × 10 − 7 at 25 GBd using a 5-tap feed-forward equalizer. This work demonstrates the first functional EO link co-integrating a graphene modulator with a BiCMOS electronic driver. By validating this wire-bonded interface, we establish a feasible and practical route towards energy-efficient, scalable photonic interconnects.

O-band transmitters are key to current and next-generation communication links. In this paper, the authors present a transmitter based on an InGaAlAs multi-quantum well (MQW) electroabsorption modulated laser (EML) and a 130 nm SiGe BiCMOS driver integrated circuit (IC). The functionality and architecture of both ICs are discussed, including the co-design aspects deriving from the DC-coupled interface, with a particular focus on the driver’s high immunity to the EAM photocurrent and capability to supply a very wide bias voltage range to the EAM. The proposed transmitter is able to send 60 GBd PAM4 signals with an extinction ratio (ER) of 8 dB at a power efficiency of 4.3 pJ/bit. Additionally, it is able to transmit up to 80 GBd NRZ signals and is even sufficiently linear to transmit PAM8 signals at 40 GBd, showcasing the transmitter potential in a wide range of applications.

This article presents a closed-loop type burst-mode clock and data recovery (BM-CDR) circuit with fast phase offset detection using 8/3x-fractional oversampling in the periodic preamble. The proposed phase offset detector achieves a resolution of 1/8 unit intervals (UIs) with a detection time of 4 UIs. A 2x-oversampling closed-loop bang-bang CDR is performed after the phase offset detection to provide jitter filtering. The switching between these two different oversampling ratios is realized in a single multi-phase clock generator (MPCG) by changing the duty-cycle in four differential quarter-rate clocks. Furthermore, fast duty-cycle switching (DCS) is introduced in the injection-locked ring oscillator (ILRO) design to speed up the transition from one sampling ratio to another. A prototype fabricated in 28-nm CMOS achieves a locking time of 1.6 ns at 30-Gb/s data rate, a BER of 1E-12 with a recovered clock integrated rms jitter of 398.4 fs. The jitter tolerance curve shows a corner frequency around 20 MHz with a 20-dB/dec slope in the low-frequency region. The receiver including the proposed CDR consumes 75.53 mW with 0.9-V supply and occupies an area of 0.148 mm2.

This article presents a radiation-hardened-by-process 56 Gbps 56 Gbps electro-absorption modulator driver designed in a 130nm SiGe BiCMOS technology for application in optical intra-satellite links. Details of the driver architecture are provided, along with the electrical and optical measurement setups used to evaluate its performance. To assess the vulnerability of the driver against radiation exposure in the space environment, samples were irradiated with X-rays up to a total accumulated dose of 1.2 Mrad(Si), simulating the effects of Total Ionizing Dose (TID) in orbit. Furthermore, heavy-ion experiments corroborated the driver’s resilience to Single Event Transients (SETs) across a range of linear energy transfers (LETs) from 20 to 65.2MeV cm²/mg, with a particle fluence of 1.2 × 10⁷ cm⁻². No Single Event Latchup (SEL) was observed in the irradiated samples during the heavy-ion exposure.